校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15/2026
  • 初選第二階段 6/22/2026
  • 校際選修 8/24/2026
  • 初選第三階段 8/31/2026
  • 開學後加退選 9/7/2026
  • 逾期加退選 9/21/2026
選課資源

低介電材料及製程技術

Low K Meterials and Processing

學期
106-1
學分
3 學分
當期課號
5374
永久課號
ISE5202
開課單位
工學院碩士在職專班-半導體組
授課教師
呂志鵬
校區
光復
類別
選修
上課時間表
週三
A
18:30–19:20
低介電材料及製程技術
EF201
3 節連堂
B
19:30–20:20
C
20:30–21:20

* 根據陽明交大上課時間表所列

概述

This is a unique course covering the fundamental material design, its applications and problem solving. This course is intended for graduate and senior students who have background in semiconductor processing, chemistry and physics. Major topics include: (1) RC delay in interconnects, (2) low-dielectric constant materials, (3)characterization and structure-property, (4) key processing modules such as patterning, metallization and CMP, (5) ALD technology, (6) far-backend, (7) die/package interactions and reliability, and (8) future challenges. 目標: 1. 瞭解介電材料在後段連接(Interconnects)之角色, 其物化特性,製程技術及整合 2. 瞭解介電材料front-end gate dielectrics之角色, 其物化特性,製程技術及整合 3. 後段連接製程技術 4. 藉由實例討論及分組專題製作,增進團隊分工合作素養, 以應付未來產業的挑戰 5. 輔助未來相關就業之準備 Note: 1. This course is recognized by NDL (Nano-Device Labs) as the prerequisite to use its facility. 2. The lecture notes have been updated to reflect the latest 14 nm technology. Double patterning, EUV, dual hardmask and metal hardmask integration schemes, extreme low-k, air-gap, self-forming-barrier, metal cap, fan-out wafer level package have been updated and added this year.

先修科目

None

教學方式

助教 (Teaching Assistant): Wei-Yuan Chang (EF702) ext. 55396

評分方式

No exam. 7 assigned homework (70%) (1-2 students are invited to present their homework and discussion) Final team project assignment: 30% (Presentation and report) Note: 1 Report should follow the format of J. of Applied Physics Note:2. Presentation is graded by peer (50%) and instructor (50%). with a forced distribution. Note 3 10 minutes lecture on Ethics in Science and Engineering is planned for this course in the opening session

課程大綱
  • Backend interconnect and device technology
  • Low k materials
  • characterization and structure-property
  • Processing Technologies
  • Emerging ALD technology
  • Futuristic interconnect technology
  • High-k dielectrics
週次計畫
週次主題
第 1 週Overview of Backend Interconnects
第 2 週Class will be re-scheduled
第 3 週Overview on Interconnect Delay and Technology Options
第 4 週National Holiday Mid-Autumn Festival
第 5 週Low-k Dielectric Materials: Properties and Requirements Fundamentals of Dielectrics
第 6 週Si-based Dielectric Materials – 1
第 7 週Si-based and Polymeric Dielectric Materials
第 8 週Characterization of low-k materials
第 9 週Presentation/Discussion Homework assignment
第 10 週Etch Stop and Passivation Dielectrics / Integration
第 11 週Module - Lithography
第 12 週Modules - Etch/Clean Technology
第 13 週Students' Presentation on Characterization Techniques
第 14 週Modules – Metallization (Thin film/ALD, CMP.)
第 15 週Chemical-mechanical polish (CMP)
第 16 週Futuristic technologies for Interconnects, Materials Options and Challenges
第 17 週- Materials and integration Options/Porous low-k dielectrics
第 18 週Final Presentation
教科書

Textbook: Advanced Interconnects for ULSI Technology, Edited by M.R. Baklanov, P.S. Ho, and E. Zschech, Wiley & Son, United Kingdom (2012) References: 1. Interlayer Dielectrics for Semiconductor Technologies, Eds. By S. P. Muraka, M. Eizenberg, and A.K. Sinha, Academic Press (2004) 2. Dielectric Films for Advanced Microelectronics, Eds. by Mikhail Baklanov, Karen Maex, Martin Green, John Wiley & Sons, New York (2007) 3. Silicon VLSI Technology: Fundamentals, Practice and Modeling, J.D. Plummer, M. D. Deal and P.B. Griffin, Prentice Hall, New Jersey (2000) 4. S.O. Kasap, Principles of Electronic Materials and Devices, The McGraw-Hill Company, 3rd Edition (International Edition), Singapore (2006) 5. Low Dielectric Constant Materials for IC Applications, Eds. by P.S. Ho, J. Leu and W.W. Lee, Springer Verlag (2003) 6. Class notes and literatures relevant to low-k technologies

Office Hours
地點
EF316
時間
Mondays 5-6 pm
聯絡方式
(03) 5131420