程式化邏輯系統設計
Programmable Logic System Design
| 節 | 週一 |
|---|---|
5 13:20–14:10 | 程式化邏輯系統設計 EE634 2 節連堂 |
6 14:20–15:10 | |
A 18:30–19:20 | 程式化邏輯系統設計 EE634 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
This course is teaching students the techniques on large scale logic design and familiarizing them with FPGA platform. Students will learn the use of VHDL or Verilog and digital system prototyping and simulation.
Logic Design or Digital System
2-hr lecture and 3-hr lab every week. The PPT file and experiment both will be adpoted for the explanation the content in the textbook. Teaching Assistant info.: 顏永哲, EE814, ext.54415, yanjohn888@gmail.com
(a) ten experiments (b) one final examination Evaluation: Experiment: 10 X 10 X 70%=70 points Final: 100 X 20% = 20 points Performance & Att.: 10 points
S. Brown and Z. Vranesic, “Fundamentals of Digital Logic with Verilog Design,” 3rd Edition, McGraw-Hill
- 地點
- EE740 EE814
- 時間
- (1) Wed.. X, E, F, G : 歐陽盟 (2) Wed.. X, E, F, G : 顏永哲
- 聯絡方式
- ext.31965 ext.54415