校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15/2026
  • 初選第二階段 6/22/2026
  • 校際選修 8/24/2026
  • 初選第三階段 8/31/2026
  • 開學後加退選 9/7/2026
  • 逾期加退選 9/21/2026
選課資源

積體電路設計實驗

Integrated Circuit Design Laboratory

學期
106-2
學分
3 學分
當期課號
5033
永久課號
IEE5712
開課單位
電子研究所
授課教師
李鎮宜
類別
選修
上課時間表
週三
5
13:20–14:10
積體電路設計實驗
2 節連堂
6
14:20–15:10
A
18:30–19:20
積體電路設計實驗
2 節連堂
B
19:30–20:20

* 根據陽明交大上課時間表所列

概述

This course aims to convey the senior and graudate EE students techniques to design VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone. The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC), SoCs or application processors with integrated sensors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication.

先修科目

Introduction to VLSI

教學方式

http://www.si2lab.org/course/iclab2016 Lecture at ED415 Lab at ED415

評分方式

作業部份: 10 Lab. Exercises Homeworks and Project 考試部份: project-based with on-line tests. 評量部份: 10 Lab. Exercises (60%) Homeworks and Project (30%) On-Line Test (10%) Total score is 100%

教科書

(1) "Application-Specific Integrated Circuits" by Prof. M.J.S. Smith from University of Hawaii ( Addison-Wesley, 1997, ISBN 0-201-50022-1 ). This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference. (2) "Principles of CMOS VLSI Design -- A Systems Perspective", by Neil H. Weste and Kamran Eshraghian ( 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6 ).

Office Hours
地點
ED538
時間
Every Wed. Morning from 10:00AM to 12:00AM at ED538. Prefer making appointment via email.
聯絡方式
email: cylee@faculty.nctu.edu.tw ext.: 31849