通訊系統晶片設計
Chip Design for Communication Systems
| 節 | 週一 |
|---|---|
5 13:20–14:10 | 通訊系統晶片設計 EE118 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
* Understand how digital signal processing techniques can be used in VLSI design * To be familiar with algorithm development and architecture design for base band communication ICs * Understand how to realize the theoretical results to practical applications in standards * Part I: Digital filtering in hardware ■ Interation bound ■ Pipelining and parallel processing ■ Retiming ■ Unfolding ■ Numerical Strength Reduction ■ Multirate signal processing * Part II Communication systems ■ Wireless communication channel model ■ OFDM systems ■ Synchronization ■ MIMO systems ■ MIMO Precoding ■ FFT & CORDIC ■ Channel coding
* It is recommended that students have background in digital signal processing and digital communications (Not mandatory) * Some homework may need the use of Matlab and Verilog - TAs will allocate time to teach Verilog and design tools
* Course style - The course will be presented using slides - Some homeworks require the use of Matlab and Verilog (TA will allocate time to teach Verilog and the corresponding tools) * Grading - Homework 30% (5-6 homeworks) - Midterm project 30% - Final project with presentation 40%
* Textbook: -“VLSI Digital Signal Processing Systems: Design and Implementation,” by Keshab K. Parhi ■ * References: -“Digital Signal Processing,” by A. V. Oppenheim and R. W. Schafer, Prentice Hall -“Digital Communications,” by J. G. Proakis, McGraw-Hill - Papers from IEEE