超大型積體電路系統設計
VLSI System Design and Application
學期
106-2
學分
3
學分
當期課號
5058
永久課號
ICN6592
開課單位
電控工程研究所
授課教師
趙昌博
校區
光復
類別
選修
上課時間表
| 節 | 週二 |
|---|---|
5 13:20–14:10 | 超大型積體電路系統設計 EE623 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
概述
To establish students fundamental knowledge and skill on VLSI.
先修科目
Microelectronics, Logic Design
教學方式
There will be TAs responsible for grading homeworks/exams and guiding students to do projects.
評分方式
Homeworks - 30% Projects - 40% Midterm and Final - 30% Further dicussion in class.
課程大綱
- Course Introduction
- CMOS Logics and Fabrication
- Introduction to VLSI Design
- Fundamental electrical characteristics of MOS devices and nonlinearities
- MOS Device Performance Evaluation
- Power Consumption of CMOS Circuits
- Continued Power Issues of MOS Device
- CMOS Chip Wiring Design
- CMOS Circuit Modeling
- CMOS Gates and Sequential Design
- Datapath Design
- Memories
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course Introduction |
| 第 2 週 | CMOS Logics nand Fabrication Introduction to VLSI Design |
| 第 3 週 | Mos transistor theory Fundamental electrical characteristics of MOS devices and nonlinearities |
| 第 4 週 | Mos transistor theory Fundamental electrical characteristics of MOS devices and nonlinearities |
| 第 5 週 | Delay - Logical effort, RC Delay model |
| 第 6 週 | Delay - Logical effort, RC Delay model Power - Consumption of CMOS Circuits, Energy-Delay Optimization |
| 第 7 週 | Power - Consumption of CMOS Circuits, Energy-Delay Optimization Power management |
| 第 8 週 | Midterm Exam |
| 第 9 週 | Combinational Circuit Design |
| 第 10 週 | Combinational Circuit Design CMOS Gates and Sequential Design |
| 第 11 週 | Continued on Sequential Design |
| 第 12 週 | Interconnect - CMOS Chip Wiring Design |
| 第 13 週 | Datapath Design |
| 第 14 週 | Datapath Design |
| 第 15 週 | SRAM |
| 第 16 週 | SRAM |
| 第 17 週 | Final exam |
| 第 18 週 |
教科書
N. H. E. Weste and David M. Harris, "Integrated Circuit Design," Fourth Edition, Pearson Education Inc., Addison-Wesley, 2011. Sung-Mo Kang, CMOS Digital Integrated Circuits: Analysis and Design, 3/e
Office Hours
- 地點
- EE Room. 735
- 時間
- 16:30 - 18:20, every Wed.
- 聯絡方式
- (03)5131377, 校內分機