邏輯設計及其安全防護
Logic Design and Design for Security
| 節 | 週二 | 週四 |
|---|---|---|
3 10:10–11:00 | 邏輯設計及其安全防護 ED305 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 邏輯設計及其安全防護 ED305 |
* 根據陽明交大上課時間表所列
*** A major part of this course is about the design of a "Silicon Compiler" (矽編譯器), which converts/compiles hardware description language (such as Verilog or VHDL) code into logic (gates). This is a SOFTWARE class (same as the well-known compiler class) about designing tools for HDL-to-logic compilation/optimization, functional verification/simulation, etc, INSTEAD OF A HARDWARE class about designing integrated circuits (ICs) by playing with transistors, resistors, capacitors, etc. *** This an upper-undergraduate or graduate-level course for students interested in the applied algorithms for computational logic design, optimization, and protection (from the security perspective). These problems may involve more than a million logic gates and thus need to be addressed by developing sophisticated software tools. The purpose of this course is to get students to look into the algorithms inside the tools and see what makes them work, effectively and efficiently, for very-large-scale and complex logic problems. The course will require students not only experiment with a few real tools but also to build simplified versions of these tools.
Programming in C/C++ (required) Digital Circuit Design (preferred but not required) Data Structures and Algorithms (preferred but not required) Target audience: CS/EE undergraduate/graduate students who are - interested in tools that automate the design of digital circuits, or - interested in data structures and algorithms that solve complex problems, or - working on electronic design automation (EDA) or computer-aided design (CAD) for VLSI
http://e3.nctu.edu.tw/
Term Project: 35% (2+1 milestones), see "http://zh.wikipedia.org/wiki/布尔可满足性问题" for a preliminary idea about the project. Homework: 15% (3 assignments) Exams: 40% (2 exams) Participation: 10%
| 週次 | 主題 |
|---|---|
| 第 1 週 | Syllabus and Introduction |
| 第 2 週 | Logic Design Basics and Computer Arithmetic |
| 第 3 週 | Boolean Algebra and Manipulation *** Homework 1 out *** |
| 第 4 週 | Binary Decision Diagrams |
| 第 5 週 | Binary Decision Diagrams |
| 第 6 週 | Binary Decision Diagrams Boolean Satisfiability *** Term Project - Milestone 1 out (due in 2 weeks, 15% - basic features) *** |
| 第 7 週 | Boolean Satisfiability *** Homework 2 out *** |
| 第 8 週 | Boolean Satisfiability *** Term Project - Milestone 2 out (due in 3 weeks, 15% - advanced features) *** |
| 第 9 週 | Logic Simulation and Minimization *** Midterm Exam (20%) *** |
| 第 10 週 | Timing Analysis and Optimization - Static Timing Analysis |
| 第 11 週 | Timing Analysis and Optimization - Technology Mapping |
| 第 12 週 | Logic Design for Security *** Term Project - Milestone 3 out (due in 4 weeks, 5-10% - your adds-on) *** |
| 第 13 週 | Trusted Logic Design - IC/IP Protection *** Homework 3 out *** |
| 第 14 週 | Logic Locking - Encryption/Decryption |
| 第 15 週 | Watermarking and Fingerprinting |
| 第 16 週 | Hardware Trojan Horses (Presentation) |
| 第 17 週 | Miscellaneous (Presentation) |
| 第 18 週 | *** Final Exam (20%) *** |
No required textbook
- 地點
- EC530
- 時間
- Thursday after class (4:30pm ~ 5:30pm) and by appointment
- 聯絡方式
- Tel: 54734 (校內分機) E-mail: kcw@cs.nctu.edu.tw