數位電路與系統
Digital Circuits and Systems
| 節 | 週一 | 週五 |
|---|---|---|
2 09:00–09:50 | 數位電路與系統 ED116 | |
5 13:20–14:10 | 數位電路與系統 ED116 2 節連堂 | |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
This course is intended to teach undergraduate students to understand and design digital systems. The course contents cover those skills needed for current industrial digital system design using Verilog-HDL and modern CAD tools. Particular attention is paid to system level issues including factoring and partitioning digital systems, interface design, and interface timing. Topics needed for a deep understanding of digital circuits, such as timing analysis, metastability, and synchronization, will also be covered. Upon completion of this-semester course, students should be well-prepared to practice digital design in industry. They will have all of the tools they need for contemporary practice. And the experience will come with time.
logic design
All materials will be available on NCTU new e3 web site. e3new.nctu.edu.tw
Exams: one final exam (26%) (Closed book) mini-online lab and test (14%) 每周五早上 B,於ED415 1 HWs on combinational logic , 4 HWs on sequential logic on Verilog-HDL (25%, each 5 points), one online test (10% ) final-project (20%) classroom participation and test (5%)
- Verilog
- Verilog
- Testbench design
- Coding style and Verification
- Single cycle MIPS
- Pipeline architecture
- Timing and synthesis
| 週次 | 主題 |
|---|---|
| 第 1 週 | introduction |
| 第 2 週 | Verilog overview 3/1 Holiday |
| 第 3 週 | Verilog overview |
| 第 4 週 | modeling combinational logic |
| 第 5 週 | model sequential logic |
| 第 6 週 | testbench programming |
| 第 7 週 | arithmetic |
| 第 8 週 | 4/8 Holiday model datapath FSM |
| 第 9 週 | factor FSM |
| 第 10 週 | microcode |
| 第 11 週 | pipeline |
| 第 12 週 | timing |
| 第 13 週 | metastability |
| 第 14 週 | system level design |
| 第 15 週 | Verification and testing |
| 第 16 週 | Final exam 6/7 Holiday |
| 第 17 週 | online test |
| 第 18 週 | Final project demo |
Textbook. Digital Design: a systems approach by William J. Dally and R. Curtis Harting Cambridge, University Press Reference book: 1. Introduction to Logic Circuits & Logic Design with Verilog, by Brock J. LaMeres, Springer 2. Verilog HDL Primer
- 地點
- ED406
- 時間
- 1 GH, please make an appointment in advance.
- 聯絡方式
- TEL: 54243 e-mail: tschang@mail.nctu.edu.tw