數位電路設計(英文授課)
Digital Circuit Design
| 節 | 週三 | 週五 |
|---|---|---|
3 10:10–11:00 | 數位電路設計(英文授課) EC115 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 數位電路設計(英文授課) EC115 |
* 根據陽明交大上課時間表所列
本課程目標是介紹數位系統如數位電子計算機中所使用數位電路的邏輯設計的基礎觀念以及使用的基本工具。內容包括:數位系統與二進數字、布林代數與邏輯閘、閘層次最簡化、組合邏輯、同步循序邏輯、以及暫存器與計數器。 This course is aimed at introducing the fundamental concepts and the basic tools used in the logic design of digital circuits in digital systems such as a digital electronic computer. Contents include: Digital Systems and Binary Numbers, Boolean Algebra and Logic Gates, Gate-Level Minimization, Combinational Logic, Synchronous Sequential Logic, and Registers and Counters.
無/nil
教學以課堂講授為主;課程相關資料與訊息將利用e3網路教學平台傳遞 This course will be conducted through classroom lectures. Related materials and information will be posted on campus e3 website
1. 三次正式筆試,每次涵蓋課程1/3內容,於學期第六、十二及十八週的週三課堂上舉行。 2. 評分方式:平時抽考及課堂表現:25%;正式考試:25%×3=75%。(以上僅為建議;將與修課同學商定之。) 1. Three formal written examinations, each covering a third of the course contents, and are to be taken in the Wednesday class sessions in the 6th, 12th, and 18th week of the semester. 2. Grading policy: Pop quizzes and in-class performance 25%; formal written exams 25%×3=75%. (Above is suggestion only, and is to be finalized with class attendees.)
- Boolean Algebra and Logic Gates
- Gate-Level Minimization
- Combinational Logic
- Synchronous Sequential Logic
- Registers and Counters
- Memory and Programmable logic
- Design at the Register Transfer Level
- Digital Systems and Binary Numbers
| 週次 | 主題 |
|---|---|
| 第 1 週 | Chapter 1 Digital Systems and Binary Numbers |
| 第 2 週 | Chapter 1 Digital Systems and Binary Numbers Chapter 2 Boolean Algebra and Logic Gates |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates |
| 第 4 週 | Chapter 2 Boolean Algebra and Logic Gates Chapter 3 Gate-Level Minimization |
| 第 5 週 | Chapter 3 Gate-Level Minimization |
| 第 6 週 | Examination I Chapter 3 Gate-Level Minimization |
| 第 7 週 | Chapter 3 Gate-Level Minimization |
| 第 8 週 | Chapter 4 Combinational Logic |
| 第 9 週 | Chapter 4 Combinational Logic |
| 第 10 週 | Chapter 5 Synchronous Sequential Logic |
| 第 11 週 | Chapter 5 Synchronous Sequential Logic |
| 第 12 週 | Examination II Chapter 5 Synchronous Sequential Logic |
| 第 13 週 | Chapter 6 Registers and Counters |
| 第 14 週 | Chapter 6 Registers and Counters |
| 第 15 週 | Chapter 7 Memory and Programmable logic |
| 第 16 週 | Chapter 7 Memory and Programmable logic |
| 第 17 週 | Chapter 7 Memory and Programmable logic Chapter 8 Design at the Register Transfer Level |
| 第 18 週 | Examination III Chapter 8 Design at the Register Transfer Level |
M. Morris Mano and Michael D. Ciletti, “Digital Design with An Introduction to The Verilog HDL,” 5th ed., 2013, Pearson Education Limited (or the similar)
- 地點
- EC524 and TA's offices
- 時間
- 上課後再與修課學生議定之 To be determined with course attendees
- 聯絡方式
- (03)573-1828 (or campus extension 31828) cpchung@cs.nctu.edu.tw Campus e3 website