低介電材料及製程技術
Low K Meterials and Processing
| 節 | 週一 |
|---|---|
A 18:30–19:20 | 低介電材料及製程技術 EF201 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
This is a unique course covering the fundamental material design, its applications and problem solving. This course is intended for graduate and senior students who have background in semiconductor processing, chemistry and physics. Major topics include: (1) RC delay in interconnects, (2) low-dielectric constant materials, (3)characterization and structure-property, (4) key processing modules such as patterning, metallization and CMP, (5) ALD technology, (6) far-backend, (7) die/package interactions and reliability, and (8) future challenges. 目標: 1. 瞭解介電材料在後段連接(Interconnects)之角色, 其物化特性,製程技術及整合 2. 瞭解介電材料front-end gate dielectrics之角色, 其物化特性,製程技術及整合 3. 後段連接製程技術 4. 藉由實例討論及分組專題製作,增進團隊分工合作素養, 以應付未來產業的挑戰 5. 輔助未來相關就業之準備 Note: 1. This course is recognized by NDL (Nano-Device Labs) as the prerequisite to use its facility. 2. The lecture notes have been updated to reflect the latest 14 nm technology. Double patterning, EUV, dual hardmask and metal hardmask integration schemes, extreme low-k, air-gap, self-forming-barrier, metal cap, fan-out wafer level package have been updated and added this year.
None
助教 (Teaching Assistant): 吳禹萱 Cindy Wu (EF702) ext. 55326 EMail: hsuan5276@gmail.com
No exam. 7 assigned homework (70%) (1-2 students are invited to present their homework and discussion) Final team project assignment: 30% (Presentation and report) Note: 1 Report should follow the format of J. of Applied Physics Note:2. Presentation is graded by peer (50%) and instructor (50%). with a forced distribution. Note 3 10 minutes lecture on Ethics in Science and Engineering is planned for this course in the opening session
- Backend interconnect and device technology
- Low k materials
- characterization and structure-property
- Processing Technologies
- Emerging ALD technology
- Futuristic interconnect technology
- High-k dielectrics
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1. Course Outline/Syllabus 2. Overview of Backend Interconnects |
| 第 2 週 | Interconnect Overview: Trends, Challenges, and Technology Options |
| 第 3 週 | Technology Solutions for Reff scaling - Copper Metallization |
| 第 4 週 | Technology Solutions for Reff scaling - Technology Options |
| 第 5 週 | Technology Solutions for keff scaling - Low-k Dielectrics |
| 第 6 週 | Technology Solutions for keff scaling - Integration issues and Technology Options |
| 第 7 週 | Materials Characterization and Metrology |
| 第 8 週 | University Holiday |
| 第 9 週 | Presentation/Discussion Homework assignment |
| 第 10 週 | Module – Lithography (1) |
| 第 11 週 | Module - Lithography (2) |
| 第 12 週 | Module – Chemical Mechanical Planarization (CMP) |
| 第 13 週 | Module - Atomic Layer Deposition |
| 第 14 週 | Modules – Plasma Etch/Clean Technology (I) |
| 第 15 週 | Modules - Etch/Clean Technology (II) / Atomic Layer Etching (ALE) |
| 第 16 週 | Low-k Packaging and Emerging Packaging Technology |
| 第 17 週 | Final Presentation and Report |
| 第 18 週 | Final Presentation and Report |
Textbook: Advanced Interconnects for ULSI Technology, Edited by M.R. Baklanov, P.S. Ho, and E. Zschech, Wiley & Son, United Kingdom (2012) References: 1. Interlayer Dielectrics for Semiconductor Technologies, Eds. By S. P. Muraka, M. Eizenberg, and A.K. Sinha, Academic Press (2004) 2. Dielectric Films for Advanced Microelectronics, Eds. by Mikhail Baklanov, Karen Maex, Martin Green, John Wiley & Sons, New York (2007) 3. Silicon VLSI Technology: Fundamentals, Practice and Modeling, J.D. Plummer, M. D. Deal and P.B. Griffin, Prentice Hall, New Jersey (2000) 4. S.O. Kasap, Principles of Electronic Materials and Devices, The McGraw-Hill Company, 3rd Edition (International Edition), Singapore (2006) 5. Low Dielectric Constant Materials for IC Applications, Eds. by P.S. Ho, J. Leu and W.W. Lee, Springer Verlag (2003) 6. Class notes and literatures relevant to low-k technologies
- 地點
- EF316
- 時間
- Mondays 5-6 pm
- 聯絡方式
- (03) 5131420