半導體實驗
Semiconductor Laboratory
| 節 | 週三 |
|---|---|
5 13:20–14:10 | 半導體實驗 LAB 2 節連堂 |
6 14:20–15:10 | |
A 18:30–19:20 | 半導體實驗 LAB 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
This course is designed for the students who are interested in the semiconductor device fabrication with the corresponding process module. In this course, there are total ten units as follows: History of Nano Facility Center (NFC) and Semiconductor Lab. Clean room environment &Safety issues Process Integration Clean process Oxidation process Lithography process Etch process Doping process Deposition process MOS capacitor and P-N junction measurement
No prerequisites
MOS Capacitor 3片4吋完整片,正面鍍鋁之後各分為四片,一人一個1/4片,另兩片備用。 P-N Junction 4片4吋完整片,長Field Oxide之後,其中三片各分為四小片,一人一個1/4片,另兩個1/4片以及一片完整片跟隨製程備用。 自行保管自己的試片,助教會提供容器,每次實作課請帶至實驗室。 遺失或未攜帶試片,第一次扣學期總分5分,第二次扣10分,第三次扣20分並不予補發。
期末考40分 教室課1-10單元。 考試日期103.06.24。 實作表現20分 由各組助教評定,不遲到早退為15分。 實作期間104.03.11-103.06.17。 期末報告40分 一人一份,不限頁數,格式不拘。 內容必須包含製程條件、事件紀錄、結果討論。 In the final project, the students will finish the fabrication and characterization of a MOS capacitor and PN junction
| 週次 | 主題 |
|---|---|
| 第 1 週 | History of Nano Facility Center (NFC) and Semiconductor Lab. |
| 第 2 週 | Clean room environment &Safety issues |
| 第 3 週 | Process Integration |
| 第 4 週 | Clean process |
| 第 5 週 | Oxidation process |
| 第 6 週 | Lithography process |
| 第 7 週 | |
| 第 8 週 | Etch process |
| 第 9 週 | Doping process |
| 第 10 週 | Deposition process |
| 第 11 週 | MOS capacitor and P-N junction measurement |
Handouts, Reference list: Hong Xiao, “Introduction to Semiconductor Manufacturing Technology”, 2000, Prentice Hall. J. D. Plummer, M. D. Deal, and P. B. Griffin, “Silicon VLSI Technology-Fundamentals, Practice and Modeling”, 2000, Prentice Hall. S. M. Sze, “Semiconductor Devices Physics and Technology”, 2nd Ed., 2002, J. Wiley & Sons Inc. Semiconductor International Solid State Technology
- 地點
- ED640
- 時間
- Wed. 1:30-3:00pm
- 聯絡方式
- ytcheng@mail.nctu.edu.tw