校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15/2026
  • 初選第二階段 6/22/2026
  • 校際選修 8/24/2026
  • 初選第三階段 8/31/2026
  • 開學後加退選 9/7/2026
  • 逾期加退選 9/21/2026
選課資源

電腦輔助電路設計

Computer Aided Circuits Design

學期
108-1
學分
3 學分
當期課號
5244
永久課號
ILP5135
開課單位
照明與能源光電研究所
授課教師
林秀菊
類別
選修
上課時間表
週四
2
09:00–09:50
電腦輔助電路設計
CM224
3 節連堂
3
10:10–11:00
4
11:10–12:00

* 根據陽明交大上課時間表所列

先修科目

1. Logic Design or Digital System Design 2. Program Design ( C or C++ or MatLab ) 3. Installation of Downloadable Quartus II web edition & ModelSIM software

教學方式

TA : 06-3032121 ext 57843

評分方式

Midterm 30% Final oral present ( term project or paper survey & report ) 30% Others ( participation 10%、Homework & Lab 30% ) 40%

週次計畫
週次主題
第 1 週Introduction to course
第 2 週Introduction to Computer Aided circuit Design and HDL
第 3 週Basic Language Elements
第 4 週Dataflow model / Installation, Setting, and Operation of Quartus II & ModelSim
第 5 週(Holiday)
第 6 週Behavior model
第 7 週Structure model
第 8 週Subprogram and packages
第 9 週Mid Term: pencil test & hands-on project exam
第 10 週Advanced Features of VHDL
第 11 週Registers, Counters and Finite State Machines
第 12 週Programmable Logic and Storage Devices
第 13 週Area and Speed Optimization for Programmable Logic Devices
第 14 週Test Bench
第 15 週Cell-Based Design Concept
第 16 週Preparation for Project Demo & Written Report ( or Assigned Paper Survey, Presentation & Written Report )
第 17 週Final Exam (1/2): Either Project Demo & Written Report or Assigned Paper Survey, Present & Written Report
第 18 週Final Exam (2/2): Either Project Demo & Written Report or Assigned Paper Survey, Present & Written Report
教科書

※Reference : ○Digital system Design Using VHDL, Roth and John ○Embedded SoPC Design with Nios II Processor and VHDL Examples, Pong P. Chu, Wiley, 2011 , 1st ed. VHDL Primer, J. Bhasker ○Advanced Digital Design with the Verilog HDL, M.D. Ciletti

Office Hours
地點
Room 326@CM Building, Tainan
時間
Wed 10:00-12:00
聯絡方式
Dr. Lin : 06-3032121 ext 57781