記憶體電路及系統設計

Memory Circuits and System

學期

108-2

學分

3 學分

當期課號

5225

永久課號

CST5037

開課單位

國際半導體產業學院碩士班

授課教師

黃柏蒼

校區

光復

類別

選修

上課時間表

節	週二
2 09:00–09:50	記憶體電路及系統設計 EE118 3 節連堂
3 10:10–11:00
4 11:10–12:00

* 根據陽明交大上課時間表所列

概述

The goal of this course aims to learn the fundamental memory circuits and to gain the basic understanding of hierarchy memory system design methodology. The first part of the course focuses on the embedded-memory circuit design from latches, register file, SRAM, CAM to embedded DRAM and embedded non-volatile memory. We then discuss the design challenges and techniques of high-performance SRAM in nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage and degradation of noise margin due to Vt scatter are addressed. Design directions and leakage/variation/degradation tolerant SRAM circuit techniques to mitigate various performance and reliability constraints are discussed and examples are given and merits discussed. Alternative cell structures for low-voltage SRAM, such as asymmetrical SRAM, 7T, and 8T SRAMs, which decouple the cell storage node from the Read-disturb and half-select disturb to improve the static noise margin (SNM) are addressed. Some design issues and opportunities in advanced technologies are illustrated. The second part of the course covers the basics of DRAM, NVRAM, MRAM, PRAM (or PCM), and RRAM (Resistive RAM). It is intended to introduce the students to the basic idea, cell structure, and sensing schemes of these memories. The third part of this course is to discuss the hierarchy memory system from the aspect of applications, including memory interface, 3D memory, memory coherence and in-memory computing.

先修科目

Electronics Circuit Theory

教學方式

https://e3new.nctu.edu.tw/login/index.php

評分方式

10% Class participation 40% Exercises 10% Midterm (Proposal for the final project) 15% Final project presentation 25% Final project report

週次計畫

週次	主題
第 1 週	Overview of Semiconductor Memory
第 2 週	Introduction to Memory System and Memory Hierarchy
第 3 週	Design of Single-Bit Memory (Latch & Flip-flop)
第 4 週	SRAM Design – Cell Design
第 5 週	SRAM Design – Peripheral Circuits
第 6 週	SRAM Design – Read/Write Assist Circuits and variation-tolerant design techniques
第 7 週	Low-Power SRAM and SRAM in advanced technologies
第 8 週	Content-Addressable Memory
第 9 週	FIFO, Dual-port SRAM and Register-File
第 10 週	Embedded DRAM and Embedded non-volatile memory
第 11 週	Off-Chip Memory Interfaces
第 12 週	DRAM – Memory Organization
第 13 週	DRAM – Memory Access protocol and memory controller
第 14 週	3D Memory and High-Bandwidth Memory
第 15 週	Non-Volatile Memory
第 16 週	Energy-Efficient Memory Hierarchy for Deep Learning
第 17 週	In-Memory Computing

教科書

Class notes on the website, and no textbook. The class materials are mainly based on papers published at international conferences and journals in recent years and supplemented with materials from tutorials. All materials will be distributed and posted in the web as well. Reference Books [1] B. Jacob et al, “Memory Systems- Cache, DRAM and Disk”, Morgan Kaufmann 2008 [2] K Itoh, VLSI Memory Chip Design”, Springer 2001 [3] B Keeth et al, “DRAM Circuit Design: Fundamentals and High Speed Topics”, 2007 [4] G. Campardo et al, “VLSI Design of Non-Volatile Memories”, Springer 2004 [5] C. Kim and H. Lee, “High-Bandwidth Memory Interface”, Springer 2013 [6] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, “Digital Integrated Circuits”, 2004

Office Hours

地點: MIRC 301
時間: After class or by appointment
聯絡方式: By email