超大型積體電路設計導論

This course aims to convey junior EE students techniques to analyze and design system by means of VLSI technology and CAD tools. Starting from VLSI process technology and transistor's behavior. an indepth discussion covering circuit, logic, and subsystem designs will be presented. Upon completion of the course, the student will be able to design system-level IC (SLIC) based on available VLSI technology and CAD tools. As such he/she will be able to work in a team of designers or stand alone to meet system-level specifications. The course offers a complete yet accessible introduction to crosstalk models and optimization. It covers minimizing power consumption at every level of abstraction, from circuits to architecture and new insights into design-for-testability (DFT) techniques that maximize quality despite quicker turnarounds. It also presents detailed coverage of the algorithms underlying contemporary VLSI computer-aided design (CAD) software, so designers can understand their tools no matter which ones they choose. This course mainly contains 4 topics which are essential to the practice of VLSI design as a system design discipline. They are given below and will be addressed in more detail during lecture and discussion. Transistor modeling and physical design constraints Basic circuit and logic designs Data path and sub-system designs Design methodology for architecture optimization, testing and low-power

logic design, digital systems, and Electronics (I)

Week 1: Course outline and Introduction Week 2: CMOS Transistors and Behaviors Week 3: Logic Effort and Interconnects Week 4: SPICE simulation and Lab. 1 introduction (SPICE Simulator) Week 5: Logic gates and families Week 6: Circuit Families and Lab. 2 introduction (Layout Editor) Week 7: Sequential Circuits Week 8: Mid-Term Exam Week 9: Adders Week 10: Data Path and Other Arithmetic Operators Week 11: Storage modules and Array structures Week 12: Lab. 3 introduction (Verilog-HDL) Week 13: Design for Testability Week 14: Design for Low-Power Week 15: Design for Skew and Packaging and I/O Week 16: Other VLSI Design Issues and Final-term exam Week 17-18: Verilog-HDL and Layout for Final Project

Lab (Bonus): 10%; Exam: 60%; Term-Project: 40%

"CMOS VLSI Design—A circuits and systems Perspective" by Neil H.E. Weste and David Harris. (3rd Edition from Addison Wesley, ISBN:0-321-26977-2)

地點

ED 538

時間

Every Wed. Morning from 10:30 to 12:00.

聯絡方式

ext: 31849; email: cylee@faculty.nctu.edu.tw