微處理機系統原理與實作(英文授課)
Microprocessor Systems: Principles andImplementation
| 節 | 週二 | 週五 |
|---|---|---|
3 10:10–11:00 | 微處理機系統原理與實作(英文授課) ED302 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 微處理機系統原理與實作(英文授課) ED302 |
* 根據陽明交大上課時間表所列
The course will cover the architecture details of a microprocessor SoC. The open-source application processor, Aquila, developed by the EISLab in the Computer Science Department at NCTU will be used as the reference design. Aquila is a RISC-V RV32-IMA compatible processor that is capable of running official RISC-V system software, such as the FreeRTOS real-time operating system. The RTL model of Aquila is written in Verilog and it can be synthesized on an FPGA for full-system verification. In this course, Aquila will be used to teach students the design details of a microprocessor hardware-software system in the real world.
C and Verilog programming languages. Digital Designs.
There would be six graded homework. For each homework, you must modify the open-source HW-SW system of Aquila using both Verilog and C programming languages to achieve some goals. Your modification must be verified on a Xilinx Artix-7 XC7A35T FPGA development board. You have to type out a report on your implementation as well. The overall grades will be 80% based on homework and 20% based on class participation (discussions).
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction to the Course, Tools, and Platform |
| 第 2 週 | I/O Subsystem of microprocessors |
| 第 2 週 | Memory subsystems of microprocessors |
| 第 2 週 | Microarchitecture of Aquila |
| 第 2 週 | Microprocessor Design: History and Review |
| 第 2 週 | RISC-V Instruction Set Architecture |
| 第 3 週 | Multicore organization of microprocessors |
| 第 3 週 | Operating system interface design |
None.
- 地點
- EC718
- 時間
- Tue. EF. and Fri. B.
- 聯絡方式
- Phone extension: 31628 email: cjtsai@cs.nctu.edu.tw