數位電路與系統
Digital Circuits and Systems
| 節 | 週四 | 週五 |
|---|---|---|
5 13:20–14:10 | 數位電路與系統 EDB26 2 節連堂 | |
6 14:20–15:10 | ||
7 15:30–16:20 | 數位電路與系統 EDB26 |
* 根據陽明交大上課時間表所列
This course is intended to teach undergraduate students to understand and design digital systems. The course contents cover those skills needed for current industrial digital system design using Verilog-HDL and modern CAD tools. Particular attention is paid to system level issues including factoring and partitioning digital systems, interface design, and interface timing. Topics needed for a deep understanding of digital circuits, such as timing analysis, metastability, and synchronization, will also be covered. Upon completion of this-semester course, students should be well-prepared to practice digital design in industry. They will have all of the tools they need for contemporary practice. And the experience will come with time. 本課程不但教你用Verilog ,讓你會做IC設計,還教你什麼是好的IC設計。 今年課程有FPGA 實作。 沒修過logic design,請勿修課。
logic design
All materials will be available on NYCU new e3 web site. e3.nycu.edu.tw 如因疫情停課,請上e3.nycu.edu.tw 看錄影。實作課遠端連線,TA線上接受提問(週四上課時間)。 配合疫情,若遠端上課,學校要求每堂課要點名,請配合連上e3.nycu.edu.tw 點名系統。
Exams: one final exam (26%) (Closed book) 實作課 mini-online lab and test (10%) 每周四下午第七節,於ED415/ED414/ED417B (except the first week) 1 HWs on combinational logic , 4 HWs on sequential logic on Verilog-HDL and FPGA (25%, each 5 points), one online test (10% ) final-project (20%) classroom participation (4%) and short midterm test (5%)
- Verilog
- Verilog
- Testbench design
- Coding style and Verification
- Single cycle MIPS
- Pipeline architecture
- Timing and synthesis
| 週次 | 主題 |
|---|---|
| 第 1 週 | introduction |
| 第 2 週 | Verilog overview |
| 第 3 週 | Verilog overview |
| 第 4 週 | modeling combinational logic |
| 第 5 週 | model sequential logic |
| 第 6 週 | 4/2 holiday testbench programming |
| 第 7 週 | arithmetic |
| 第 8 週 | model datapath FSM (期中考周,照常上課) Short midterm test |
| 第 9 週 | factor FSM |
| 第 10 週 | microcode |
| 第 11 週 | pipeline |
| 第 12 週 | timing/metastability |
| 第 13 週 | system level design |
| 第 14 週 | Verification and testing |
| 第 15 週 | Final exam |
| 第 16 週 | online test |
| 第 17 週 | final project demo |
| 第 18 週 | Final project demo |
Textbook. Digital Design: a systems approach by William J. Dally and R. Curtis Harting Cambridge, University Press Reference book: 1. Introduction to Logic Circuits & Logic Design with Verilog, by Brock J. LaMeres, Springer 2. Verilog HDL Primer
- 地點
- ED406
- 時間
- 4 GH, please make an appointment in advance.
- 聯絡方式
- TEL: 54243 e-mail: tschang@nycu.edu.tw