數位電路設計(英文授課)
Digital Circuit Design
學期
110-2
學分
3
學分
當期課號
1174
永久課號
DCP1247
開課單位
資訊學院共同課程
授課教師
單智君
校區
光復
類別
必修
上課時間表
| 節 | 週三 |
|---|---|
3 10:10–11:00 | 數位電路設計(英文授課) EC122 2 節連堂 |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
概述
This course is aimed at introducing the fundamental concepts and methods and the basic tools used in the logic design of digital circuits. (本課程主要介紹數位電路中邏輯設計的重要觀念與方法及基本工具)
教學方式
Refer to https://e3.nycu.edu.tw for the related data and information, e.g.s, slides, schedule, announcements, etc, of the course. 課程相關資料與訊息(如:講義、進度、公告等)公佈在網路教學平台 http://e3.nycu.edu.tw
評分方式
Exams: 60-80% (3 exams) Quizzes/Homework/Implementation/Participation: 20-40%
課程大綱
- Digital Systems and Binary Numbers
- Boolean Algebra and Logic Gates
- Gate-Level Minimization
- Combinational Logic
- Synchronous Sequential Logic
- Registers ad Counters
- Memory and Programmable Logic
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Syllabus Chapter 1 Digital Systems and Binary Numbers |
| 第 2 週 | Chapter 1 Digital Systems and Binary Numbers Chapter 2 Boolean Algebra and Logic Gates |
| 第 3 週 | Chapter 2 Boolean Algebra and Logic Gates |
| 第 4 週 | Chapter 2 Boolean Algebra and Logic Gates Chapter 3 Gate-Level Minimization |
| 第 5 週 | Chapter 3 Gate-Level Minimization |
| 第 6 週 | Chapter 3 Gate-Level Minimization Exam#1 |
| 第 7 週 | Chapter 4 Combinational Logic |
| 第 8 週 | Chapter 4 Combinational Logic |
| 第 9 週 | Chapter 4 Combinational Logic |
| 第 10 週 | Chapter 5 Synchronous Sequential Logic |
| 第 11 週 | Chapter 5 Synchronous Sequential Logic Exam#2 |
| 第 12 週 | Chapter 5 Synchronous Sequential Logic |
| 第 13 週 | Chapter 6 Registers ad Counters |
| 第 14 週 | Chapter 6 Registers ad Counters |
| 第 15 週 | Chapter 7 Memory and Programmable Logic |
| 第 16 週 | Exam#3 |
| 第 17 週 | Flexible Learning Week (彈性補充教學) |
| 第 18 週 | Flexible Learning Week (彈性補充教學) |
教科書
M. Morris Mano and Michael D. Ciletti, Digital Design, 6th ed. (2019), Prentice Hall.
Office Hours
- 地點
- EC516
- 時間
- TBD (開學後討論再定)
- 聯絡方式
- ext. 31832 jjshann@cs.nctu.edu.tw