VLSI實驗
VLSI Labs.
| 節 | 週五 |
|---|---|
5 13:20–14:10 | VLSI實驗 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
This lab course is an appendix to "Introduction to VLSI Design." Student who enrolls in this class must have formerly taken or is taking "Introduction to VLSI Design" simultaneously. Introductions This lab aims to convey junior EE students techniques to analyze and design system by means of VLSI technology and CAD tools. Starting from VLSI process technology and transistor's behavior, an in-depth discussion covering circuit, logic, and subsystem designs will be presented. Upon completion of the course, the student will be able to design system-level IC (SLIC) based on available VLSI technology and CAD tools. As such he/she will be able to work in a team of designers or stand alone to meet system-level specifications. Content The course offers a complete yet accessible introduction to crosstalk models and optimization. It covers minimizing power consumption at every level of abstraction, from circuits to architecture and new insights into design-for-testability (DFT) techniques that maximize quality despite quicker turnarounds. It also presents detailed coverage of the algorithms underlying contemporary VLSI computer-aided design (CAD) software, so designers can understand their tools no matter which ones they choose. This course mainly contains 4 topics which are essential to the practice of VLSI design as a system design discipline. They are given below and will be addressed in more detail during lectures and discussions. - Transistor modeling and physical design constraints - Basic circuit and logic designs - Data path and sub-system designs - Design methodology for architecture optimization, testing and low-power
Digital Logic Design, Circuit Theory, Microelectronics
VLSI實驗 EEEC20004 The lecture would be held at ED415 physically. You need to attend the first class, otherwise, you would be dropped out the course. 欲加選本課程者,請於第一堂課來課堂,其他方式概不受理。
5 Labs + Online Test + Final Project + Final Exam The detailed grading policy will be announced in the first meeting of the class. Lab Exercise x 5 (14,14,14,10,14%) Online Test (8%) Final Project (18%) Final Exam (8%) Bonus (TBD)
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course Introduction + Environment Setting |
| 第 2 週 | Digital Circuit + Introduction to Hspice tool 【Lab01】 1-bit Full-Adder + DFF (Hspice) |
| 第 3 週 | Lab01 Discussion |
| 第 4 週 | CMOS Technology + Introduction to Layout tool 【Lab02】 1-bit Full-Adder + DFF (Layout) |
| 第 5 週 | Lab01 Demo Lab02 Discussion |
| 第 6 週 | Schematic Level Design + Logic Effort and Charge Sharing 【Lab03】 4-bit Full-Adder + DFF |
| 第 7 週 | Lab02 Demo Lab03 Discussion |
| 第 8 週 | 【Online Test】 |
| 第 9 週 | Cell-based Design + Introduction to Verilog 【Lab04】 Logic Synthesis |
| 第 10 週 | Lab03 Demo Lab04 Discussion |
| 第 11 週 | Architecture Level Design / Multiplier and Adder 【Lab05】6-bit Multiplier and Accumulator |
| 第 12 週 | Lab04 Demo Lab05 Discussion |
| 第 13 週 | 【Final Project】 Pipeline MAC Design (Team work) |
| 第 14 週 | Lab05 Demo |
| 第 15 週 | Final Project Implementation |
| 第 16 週 | 【Final Exam】 |
| 第 17 週 | Final Project Implementation |
| 第 18 週 | Final Project Demo (online demo) |
No need to prepare textbooks, lab material will be announced in NEW E3 Platform. Reference textbook: "CMOS VLSI Design—A circuits and systems Perspective" by Neil H.E. Weste and David Harris. (2005 3rd Edition)(2010 4th edition)
- 地點
- ED505, EIC213, or online
- 時間
- By appointment
- 聯絡方式
- Email: hcchang.ee@nycu.edu.tw TA: lhlai@ieee.org