積體電路設計實驗

This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design the integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone. The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC) or application processors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication.

logic design, digital systems, and Electronics (I), introduction to VLSI design

Students that are interested in registering in this IC design lab, please fill out the google form below: https://docs.google.com/forms/d/e/1FAIpQLSfIUxnwVFy7V9sjWhysSxTZDL3rJHYMZiXPFSz2saj4mI4QWQ/viewform (For students from NYCU, please fill out the form with your NYCU email account.) You can only fill out this form once without any modification afterwards. Make sure you read through it carefully! If there are any new information regarding this course, we will update it on our course website: http://www.si2lab.org/course/iclab2023spring/ (We will update the website as soon as possible, but the link will not be changed.) We will send out emails to students who have been accepted into this class, and the list of students will also be updated on our course website. For the first stage of registration, we will announce the result before 1/16 on our website. We will accept students that have completed this survey before 1/12 23:59. For the second stage of registration, there will be more students accepted before 2/20. We will send out emails to those who have been accepted and update it on the website. We will accept students that have completed this survey before 2/17 23:59.

Item Times Ratio Weekly exercises 12 60% Midterm Project 1 10% Midterm Exam 1 5% Online tests 1 5% Final Exam 1 10% Final Project 1 10%

Reference books: [1] S. Churiwala and S. Garg,"Principles of VLSI RTL Design" from Springer, ISBN: 978-1-4419-9295-6. [2] M. Keating, "The Simple Art of SoC Design - Closing the Gap between RTL and ESL" from springer ISBN: 978-1-4419-8585-9. [3] James M. Lee, "Verilog? Quicstart A Practical Guide to Simulation and Synthesis in Verilog" from Springer, ISBN: 978-0-7923-7672-9. [4] M.J.S. Smith, "Application-Specific Integrated Circuits," from University of Hawaii, Addison-Wesley, 1997, ISBN 0-201-50022-1. This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference. [5] N.H. Weste and K. Eshraghian, "Principles of CMOS VLSI Design -- A Systems Perspective," 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6.

地點

ED 538 or Online

時間

Every Wed. afternoon from 16:30-18:00 (Booking via Email)

聯絡方式

ext: 31849; email: cylee@nycu.edu.tw