邏輯設計【英文班】
Logic Design
學期
112-1
學分
3
學分
當期課號
515112
永久課號
EEEC10025
開課單位
電機工程學系
授課教師
賴伯承
校區
光復
類別
必修
上課時間表
| 節 | 週二 | 週五 |
|---|---|---|
3 10:10–11:00 | 邏輯設計【英文班】 EDB27 2 節連堂 | |
4 11:10–12:00 | ||
5 13:20–14:10 | 邏輯設計【英文班】 EDB27 |
* 根據陽明交大上課時間表所列
概述
This course offers an introduction to any undergraduate who wants to understand digital systems. This course is essential for later courses in digital design, computer architecture, and design automation.
先修科目
None
評分方式
Grading Policy: Homework: 20% Quizzes: 20% Exams: 60% (Exam1: 30%, Exam2: 30%)
課程大綱
- Number Systems and Conversion
- Boolean Algebra
- Algebraic Simplification
- Applications of Boolean Algebra
- Karnaugh Maps
- Multi-Level Gate Networks NAND and NOR Gates
- Combinational Circuits Design and Simulation Using Gates
- Multiplexers, Decoders, and Programmable Logic Arrays
- Latches and Flip-Flops
- Registers and Counters
- Analysis of Clocked Sequential Networks
- Derivation of State Graphs and Tables
- Reduction of State Tables/State Assignment
- Sequential Circuit Design
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Number Systems and Conversion |
| 第 2 週 | Boolean Algebra |
| 第 3 週 | Algebraic Simplification |
| 第 4 週 | Applications of Boolean Algebra |
| 第 5 週 | Karnaugh Maps |
| 第 6 週 | Multi-Level Gate Networks NAND and NOR Gates |
| 第 7 週 | Combinational Circuits Design and Simulation Using Gates |
| 第 8 週 | Exam1 |
| 第 9 週 | Multiplexers, Decoders, and Programmable Logic Arrays |
| 第 10 週 | Latches and Flip-Flops |
| 第 11 週 | Registers and Counters |
| 第 12 週 | Analysis of Clocked Sequential Networks |
| 第 13 週 | Derivation of State Graphs and Tables |
| 第 14 週 | Reduction of State Tables/State Assignment |
| 第 15 週 | Sequential Circuit Design |
| 第 16 週 |
教科書
C. H. Roth, Jr. and L. Kinney, Fundamentals of Logic Design, 7th edition, Cengage, 2014.
Office Hours
- 地點
- ED402
- 時間
- Thursdays 3~4pm. Or by appointment.
- 聯絡方式
- bclai@nycu.edu.tw