超大型積體電路導論

This course aims to convey junior EE students techniques to analyze and design system by means of VLSI technology and CAD tools. Starting from VLSI process technology and transistor's behavior. an indepth discussion covering circuit, logic, and subsystem designs will be presented. Upon completion of the course, the student will be able to design system-level IC (SLIC) based on available VLSI technology and CAD tools. As such he/she will be able to work in a team of designers or stand alone to meet system-level specifications. The course offers a complete yet accessible introduction to crosstalk models and optimization. It covers minimizing power consumption at every level of abstraction, from circuits to architecture and new insights into design-for-testability (DFT) techniques that maximize quality despite quicker turnarounds. It also presents detailed coverage of the algorithms underlying contemporary VLSI computer-aided design (CAD) software, so designers can understand their tools no matter which ones they choose. This course mainly contains 4 topics which are essential to the practice of VLSI design as a system design discipline. They are given below and will be addressed in more detail during lecture and discussion. Transistor modeling and physical design constraints Basic circuit and logic designs Data path and sub-system designs Design methodology for architecture optimization, testing and low-power

logic design, digital systems, and Electronics (I)

各位同學好,由於希望選修VLSI的同學眾多,而實體授課教室會有座位限制,因此會由助教協助統一進行抽籤。 https://reurl.cc/eDO34b 此表單為調查選課人數/意願/學生背景調查,結果或通知請參考實驗室課程網頁: * 此表單用於調查選課意願的學生,實際結果以選課系統為準 * 請務必閱讀清楚再填寫! * 請同學以NYCU的信箱登入填寫 * 請注意:並非填寫表單完成即加簽成功,需經由統一抽籤才能加選 選課成功會”以電子郵件通知”加簽成功同學,名單也會一併公告在實驗室課程網頁 http://www.si2lab.org/course/vlsi2023/ 請務必注意資料填寫正確 若資料填寫不正確,可能導致無法通知第一堂課相關訊息 或是無法在課務系統上查詢到資料,導致加簽失敗 最新結果請依據公告更新及信件通知,請勿反覆寄信、打擾老師或助教! 請注意:並非填寫表單完成即加簽成功,需經由統一抽籤才能加簽! 請注意:並非填寫表單完成即加簽成功,需經由統一抽籤才能加簽! 請注意:並非填寫表單完成即加簽成功,需經由統一抽籤才能加簽! 本課程第一堂課為線上課程 欲加選本課程者,請於第一節課參與課程,其他方式概不受理。 第一堂 上課網址 https://nycu.webex.com/wbxmjs/joinservice/sites/nycu/meeting/download/565a7faa6a234b81a61128e42a027c21?siteurl=nycu&MTID=m553060ef4bb941a32154545909de34e4 Week 1: Course outline and Introduction Week 2: CMOS Transistors and Behaviors Week 3: Logic Effort and Interconnects Week 4: SPICE simulation and Lab. 1 introduction (SPICE Simulator) Week 5: Logic gates and families Week 6: Circuit Families Week 7: Sequential Circuits Week 8: Mid-Term Exam Week 9: Adders Week 10: Data Path and Other Arithmetic Operators Week 11: Storage modules and Array structures Week 12: Design for Testability Week 13: Design for Low-Power Week 14: Design for Skew and Packaging and I/O Week 15: Other VLSI Design Issues and FinFET Design Week 16: Final-Term Exam Week 17-18: Lab 2 on Layout for Logic Gates (Both Fully-Custom and Cell-Based Designs)

Mid/Final-Term Exam: 70%; Labs on SPICE and Logic Layout: 30%

"CMOS VLSI Design—A circuits and systems Perspective" by Neil H.E. Weste and David Harris. (3rd Edition from Addison Wesley, ISBN:0-321-26977-2)

地點

ED 538 or Online

時間

Every Wed. Afternoon from 3:30-5:00PM (Booking via Email)

聯絡方式

ext: 31849; email: cylee@nycu.edu.tw