超大型積體電路導論
Introduction to VLSI Circuits
學期
112-1
學分
3
學分
當期課號
515141
永久課號
EEEC20062
開課單位
電機工程學系
授課教師
洪浩喬
校區
光復
類別
選修
上課時間表
| 節 | 週二 | 週四 |
|---|---|---|
7 15:30–16:20 | 超大型積體電路導論 EE102 2 節連堂 | |
8 16:30–17:20 | 超大型積體電路導論 EE102 |
* 根據陽明交大上課時間表所列
概述
This course introduces CMOS VLSI manufacturing process, circuit layout, and CMOS combinational and sequential digital circuit design.
先修科目
Logic design, Microelectronic circuits I and II.
教學方式
All course related information will be announced on E3.
評分方式
小考34%、期中考33%、期末考33%
課程大綱
- Introduction
- Basic CMOS logics
- CMOS fabrication process
- Circuit layout
- CMOS transistor's characteristics
- Speed
- Logic efforts
- Interconnection
- Power
- Combination circuits
- Circuit Families
- Sequential circuit design
- Adders
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction to baisc VLSI design flow and concepts |
| 第 2 週 | Compound standard CMOS gate design |
| 第 3 週 | Introduction to how CMOS IC is fabricated and what masks are. |
| 第 4 週 | Introduction to how to draw circuit layouts |
| 第 5 週 | Transistor's I/V characteristics and nonideality |
| 第 6 週 | Estimation of digital circuit's speed |
| 第 7 週 | Handling Fan-in and Fan-out of logic gates |
| 第 8 週 | Handling Fan-in and Fan-out of logic gates mid-term exam. |
| 第 9 週 | Interconnections in IC and their influences |
| 第 10 週 | Estimation of digital circuit's power |
| 第 11 週 | Standard CMOS combinational gate design |
| 第 12 週 | Standard CMOS combinational gate design Introduction to various CMOS combinational gate families |
| 第 13 週 | Introduction to various CMOS combinational gate families |
| 第 14 週 | static and dynamic latches, flip-flops, and sequential circuit design |
| 第 15 週 | Introduction to various implementations of adders |
| 第 16 週 | Final exam. |
教科書
Neil H. E. Weste and D. M. Harris, Integrated Circuit Design, Fourth Edition, Pearson Education Inc.
Office Hours
- 地點
- EE705
- 時間
- 14:30 to 15:20, every Tuesday
- 聯絡方式
- ext. 54375 hchong@nycu.edu.tw