CMOS 元件, 可靠度, 及應用之特論

Course outline: Overview of CMOS technology Evolution – past, present, and future (driving forces: Performance, Power, Area (or functionality), and Cost -- "PPAC") Review of fundamentals: C. Hu’s textbook: Chap.1,2,4,5,6,7 (~1/2 time) Tunneling: FN and DT, and Band-to-band  HK/MG gate stack -- limitations of Poly/SiON gate stack, and implementation of HK/MG Strain engineering -- Emb-SiGe, Stress liner(s), SMT, and SPT Layout dependent effects -- local (stress, implant) and global (CMP, RTP) effects Recent efforts on FinFET and NanoSheet-FET -- IEDM & VLSI short courses by TSMC Hot carrier effects : mechanisms, damage (Qit and Qot), and lifetime prediction -- Local field Emax model, and CHE created Isub and Ig -- Improvement methodology (Emax reduction, overlap of Emax, and oxide robustness) Memory Technologies (SRAM, DRAM, charge-based NVM, and emerging memories MRAM, PcRAM, etc)

at least one entry-level semiconductor device related course better to have taken: solid-state physics, and/or quantum mechanics

Homework 5% mid-term exam 45% final exam 45% attendance and in-class responses 5%

"Modern Semiconductor Devices for Integrated Circuits" by Chenming Calvin Hu

地點

classroom assigned

時間

prior to class begin, or during breaks

聯絡方式

ic.chen.tx@gmail.com