數位電路與系統
Digital Circuits and Systems
| 節 | 週二 | 週四 |
|---|---|---|
7 15:30–16:20 | 數位電路與系統 ED713 2 節連堂 | |
8 16:30–17:20 | 數位電路與系統 ED713 2 節連堂 | |
9 17:30–18:20 |
* 根據陽明交大上課時間表所列
本課程將介紹IC設計的前段設計流程,從SystemC設計介紹起,讓學生了解如何透過摘要層(abstract level)來評估電路系統架構的優劣,接著使用Verilog-HDL來進行RTL驗證,最後進行FPGA以及邏輯閘層級(gate-level)的整合驗證。課程當中會介紹IC設計前段流程中所使用的常見電腦輔助設計(CAD)工具,並且介紹如何透過面積-時間-攻耗分析、程式設計方法等技巧來設計一個有效的數位電路。 This course will introduce the front-end digital IC design flow, starting with SystemC design. It aims to help students understand how to evaluate the merits and demerits of circuit system architectures through abstract-level analysis. Subsequently, Verilog-HDL will be used for RTL verification, followed by integration verification at the FPGA and gate-level simulation. The course will cover common Computer-Aided Design (CAD) tools used in the front-end digital IC design flow and explain how to design an effective digital circuit through ATP (Area-Timing-Power) analysis and coding style.
邏輯設計 logic design
1. 本門課因空間因素,不接受手動加簽,請直接在線上選課,不接受超過上限人數。上限人數有可能因空間關係隨時做調整。請自行注意。 2. 部分課程會採用錄影方式進行,請按公告至E3上觀看。 3. 第三周起的每周四下午為上機課程,請按公告進行。 4. 本課程鼓勵討論,但嚴禁抄襲,抄襲與被抄襲者當次作業/考試皆為0分。 1. Due to space constraints, manual add-ons are not accepted for this course. Please directly enroll online and note that exceeding the maximum number of participants is not allowed. The maximum limit may be adjusted based on the space constraints. 2. Some courses will be conducted through recorded video. Please refer to the announcements and watch on E3. 3. Starting from the third week, Thursday afternoons will switch to Lab class. Please follow the announcements for further instructions. 4. This course encourages discussion but strictly prohibits plagiarism. Both the plagiarizer and the victim of plagiarism will receive a score of zero for the respective assignment/exam.
Homework: 20% Lab: 10% Final project: 30% Midterm exam (physical): 20% Final exam (online): 20%
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction |
| 第 2 週 | Basic SystemC |
| 第 3 週 | SystemC: Module Description |
| 第 4 週 | SystemC: Basic Interface and Channel |
| 第 5 週 | Verilog-HDL: Verilog Overview |
| 第 6 週 | Verilog-HDL: Combinational Logic |
| 第 7 週 | Verilog-HDL: Sequential Logic 4/4 Holiday |
| 第 8 週 | Verilog-HDL: Testbench |
| 第 9 週 | Midterm exam |
| 第 10 週 | Synthesis and Gate-level Simulation |
| 第 11 週 | Synthesis and Gate-level Simulation |
| 第 12 週 | Satic Timing Analysis |
| 第 13 週 | Single-cycle and Pipeline MIPS Processor |
| 第 14 週 | FPGA Verification |
| 第 15 週 | Final exam |
| 第 16 週 | Take-home on-line test (6/4 15:30 - 17:20) |
1. M. Morris R. Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog 6th edition, Pearson, 2019 (ISBN: 978-1-292-23116-7) 2. David C. Black, Jack Donovan, Bill Bunton, and Anna Keist, SystemC: From the Ground Up, Springer, 2010. (ISBN: 978-0-387-69957-8)
- 地點
- ED414
- 時間
- 10 am - 12 pm, Monday
- 聯絡方式
- kcchen@nycu.edu.tw