計算機組織
Computer Organization
| 節 | 週四 |
|---|---|
5 13:20–14:10 | 計算機組織 EC022 2 節連堂 |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
This course aims to introduce the computer organization that includes CPU, memory, and cache. The Intended Lecture Outcomes (ILOs) is shown below. 1. Learn the great ideas of computer design and implementation 2. Learn the design and formats of RISC-V instruction set 3. Understand the detail of the pipelining CPU processor organization 4. Introduce the memory hierarchies (DRAM and Cache) 5. Implement a simple RISC-V CPU architecture
C programming, digital system design, and verilog programming
5 labs (60 %) 2 exams (40 %) Lab 0 Environment Setup & simple verilog practice Lab 1 Single Cycle CPU w/ Simple RISC-V Instruction Lab 2 Single Cycle CPU w/ Branch Instruction Lab 3 Pipelining CPU Lab 4 Data/Control Hazard Lab 5 Implement Cache Simulator
| 週次 | 主題 |
|---|---|
| 第 1 週 | Technology Trends and Quantitative Analaysis for Performance |
| 第 2 週 | RISC-V Instructions Sets, Part 1 |
| 第 3 週 | RISC-V Instructions Sets, Part 2 |
| 第 4 週 | RISC-V Instructions Sets, Part 3 |
| 第 5 週 | Arithmetic for Computers |
| 第 6 週 | RISC-V Single-Cycle Implementation |
| 第 7 週 | RISC-V Single-Cycle Implementation |
| 第 8 週 | Pipeline and Hazards |
| 第 9 週 | Pipeline and Hazards |
| 第 10 週 | Midterm |
| 第 11 週 | Branch Predictor |
| 第 12 週 | Memory Hierarchy - DRAM |
| 第 13 週 | Memory Hierarchy - Cache Organization |
| 第 14 週 | Memory Hierarchy - Cache Optimization |
| 第 15 週 | Data-Level Parallelism |
| 第 16 週 | Thread-Level Parallelism |
David A. Patterson, John L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, Morgan Kaufmann, 5e
- 地點
- EC707
- 時間
- 4CD
- 聯絡方式
- ttyeh@cs.nycu.edu.tw