積體電路設計實驗

This course aims to convey the senior and graudated EE students techniques to design the VLSI chips using state-of-the-art CAD tools. In addition to learning CAD tools for performance-driven and cost-effective IC designs, a top-down design flow and related environment will also be addressed. Upon completion of the course, the student will be able to design the integrated circuits and systems based on standard cell library as well as full-custom layout approaches. As such he/she will be able to work in a team of designers or stand alone. The course starts from system design specs of an application which demands the need of developing specific hardwares or application specific integrated circuits (ASIC) or application processors. Then followed by the presentation of architectural proposals, an optimal architecture leading to performance-driven and cost-effective realization can be derived based on both sampling rate and system clock rate. With the support of Verilog-HDL, designers can describe their designs either in behavioral level or structural level. Before going down to the lower level design, one has to do initial floorplan to estimate both routing style and module aspect ratio which provide some area constraints for later designs. Then the partitioned blocks can be conducted hierarchically and with the support of synthesis as well as P&R routing tools, physical layout can easily be achieved if cell-based design approach is exploited. Finally through layout verification and post-layout simulation, the design can be verified before fabrication.

logic design, digital systems, and Electronics (I), introduction to VLSI design

(1) 第一、第二、第三階段選課:開放選課且電子所、電機系、產創學院優先;不開放填寫google表單 (2) 開學後加退選階段:開放選課; (3) 未加選到同學: 開放填寫google表單且依規定加簽 依照順位排序1.電子所 2.電機系 3.相關學院 4.外系所 5.外校 進行篩選進行網路加簽,加簽總人數會經老師評估後決定最後加簽人數。 相關學院包含電機學院、資訊學院、產創學院、國半學院。如為外系所、外校欲進行加選,除填表單外,亦須提供曾修習兩門相關課程之修課成績單。若外系所、外校無提供成績單,即便選課系統選上,亦會被手動退選。相關課程:1.邏輯設計 2.數位電路與系統3.超大型積體電路設計導論(VLSI)4.數位積體電路(DIC) 加簽方式會在第一堂課時特別說明並提供表單,欲加簽同學第一堂課請務必要來。

Weekly exercises 5*12+3*1=63% Midterm Project 8% Midterm Exam 8% Online tests 5% Final Exam 8% Final Project 8% Total 100%

Reference books: [1] S. Churiwala and S. Garg,"Principles of VLSI RTL Design" from Springer, ISBN: 978-1-4419-9295-6. [2] M. Keating, "The Simple Art of SoC Design - Closing the Gap between RTL and ESL" from springer ISBN: 978-1-4419-8585-9. [3] James M. Lee, "Verilog? Quicstart A Practical Guide to Simulation and Synthesis in Verilog" from Springer, ISBN: 978-0-7923-7672-9. [4] M.J.S. Smith, "Application-Specific Integrated Circuits," from University of Hawaii, Addison-Wesley, 1997, ISBN 0-201-50022-1. This book covers a lot of design issues and related CAD tools which may interest readers and provide many details for reference. [5] N.H. Weste and K. Eshraghian, "Principles of CMOS VLSI Design -- A Systems Perspective," 2nd Edition from Addison-Wesley Publishing Company, ISBN 0-201-53376-6.

地點

ED 538 or Online

時間

Every Wed. afternoon from 16:30-18:00 (Booking via Email)

聯絡方式

Ext: 31849; Prof. email: cylee@nycu.edu.tw TA email: kenlin.ee09@nycu.edu.tw