RISC-V人工智慧運算架構與系統
AI Computing Architectures and Systems with RISC-V
| 節 | 週一 |
|---|---|
7 15:30–16:20 | RISC-V人工智慧運算架構與系統 EC114 2 節連堂 |
8 16:30–17:20 |
* 根據陽明交大上課時間表所列
AI應用的普地開花將促進全世界人工智慧加速晶片設計蓬勃發展,其中RISC-V相關軟硬體技術更是關鍵的核心。 這門課主要目標在於以國際業界實際設計範例為基礎,透過密集Lab實作方式,有系統化引導學生對整個AI系統軟體與硬體整合設計概念的掌握,逐步入門【人工智慧加速晶片設計】的領域,修課同學將具有基本的AI 運算加速的實作基礎與背景知識,鼓勵將來投入RISC-V及IC設計產業。 本課程係由林偉棻教授開設授課,與資訊學院陳添福老師研究合作。林偉棻教授將過去多年在國際IC設計大廠經驗,萃取彙整成9項實驗模組,期待使同學透過實際設計案例的實驗操作,對整個AI加速器系統有更具體的認識。 林偉棻教授共作經歷: 09/2022 – present COMPUTER ARCHITECT/ – Rivos Inc, Mountain View, CA 08/2020 – 07/2023 VISITING PROFESSOR– School of Computing, National Cheng-Kung University 09/2020 – 06/2022 COMPUTER ARCHITECT/PROJECT LEAD – Google, Taiwan 01/2019 – 06/2020 VP OF ENGINEERING– Skymizer Taiwan INC 09/2018 – 12/2018 CONSULTANT – Skymizer Taiwan INC 09/2012 – 06/2015 ADJUNCT ASSOCIATE PROFESSOR– Dept. of EE, National Cheng-Kung University 11/2010 – 09/2020 FOUNDER– Mijotech Inc, Taiwan/USA 09/2009 – 07/2010 COMPUTER ARCHITECT – Apple Corporation, Cupertino CA 04/2008 – 07/2009 COMPUTER ARCHITECT – Novafora, San Jose CA
數位電路、計算機組織、作業系統、計算機架構
本課程以系統實作為主軸,融合軟體硬體系統垂直整合與協同設計。
此課程並無其中或期末考試,共設計有9項實驗模組。
| 週次 | 主題 |
|---|---|
| 第 1 週 | Overview & Lab environment preparation |
| 第 2 週 | PartI: Software & Simulation ● Lab 1 — C programming review |
| 第 3 週 | Lecture 2: AI Chips Development Landscape and Trends ● Lab 2 — C memory management review |
| 第 4 週 | Lecture 3-1: Introduction to Assembly Language and RISC V Instruction Set Architecture |
| 第 5 週 | Lecture 3-2 - More RISC V Instructions and How to Implement Functions ● Lab 3 — RISC-V assembly |
| 第 6 週 | Lecture 4-1 - Digital Design Basics Lecture 4-2 - chisel tutorial |
| 第 7 週 | Part II: Hardware Design and Chisel Lecture 5-1 - RISC-V Instruction Formats Lecture 5-2 - Compiler/Assembler/Linker/Loader ● Lab 4 — RISC-V emulator |
| 第 8 週 | 期中周停課 |
| 第 9 週 | Lecture 6-1 - Combinational Logics Lecture 6-2 - RISC-V datapath ● Lab 5 — Chisel Tutorial && Datapath Design |
| 第 10 週 | Lecture 7-1 - FSM Design Chisel Book Chapter 8 – FSM Chisel Book Chapter9 – Part I Communicating FSM |
| 第 11 週 | Lecture 8-1 - Single-Cycle RISC-V Control Lecture 8-2 - 5-stage pipelined RISC-V Design Lab 6 Description ● Lab 6 — Finite State Machine Design |
| 第 12 週 | Part III: Introduction to AI Computing Acceleration Design Lecture 9-1 - Data-Level Parallelism Lecture 9-2 – SIMD instruction design ● Lab 7/Lab 10 — RISC-V CPU Implementation |
| 第 13 週 | Lecture 10-1 Memory-Mapped Accelerator ● Lab 8 — RISC-V standard Extension && SIMD instructions |
| 第 14 週 | Lecture 11-1 Weight-Stationary Systolic Array |
| 第 15 週 | Lecture 12-1 AXI Bus Design ● Lab 9 — Memory-Mapped I/O && Conv2D Acceleration |
| 第 16 週 | Invited talk |
| 第 17 週 |
- [Chisel 3.0 Tutorial paper] (https://inst.eecs.berkeley.edu/~cs250/sp17/handouts/chisel-tutorial.pdf) - [Digital Design in Chisel, 2nd Ed] (http://www.imm.dtu.dk/~masca/chisel-book.pdf) - [RISC-V Learning Online](https://riscv.org/risc-v-learn-online/)
- 地點
- EC424
- 時間
- TBD
- 聯絡方式
- 林偉棻: weifen.lin@gs.ncku.edu.tw 陳添福: tfchen@cs.nycu.edu.tw