積體電路之靜電防護設計特論
Special topic on ESD Protection Design in CMOS Ics
| 節 | 週四 |
|---|---|
A 18:30–19:20 | 積體電路之靜電防護設計特論 ED220 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
本課程講授積體電路與微電子系統可靠度上的一項專業技術:『靜電放電(ESD, Electrostatic Discharge)防護設計』,其中包括靜電放電工業標準、靜電放電測試方法、半導體製程因素、防護元件設計與佈局方式、靜電放電防護電路設計、全晶片防護架構設計、微電子系統(system-level)之靜電放電防護、以及閂鎖效應(Latchup)防治。
電路學, 電子學, 積體電路相關課程等。需具備「積體電路」設計、佈局、與製造的經驗或背景知識。
課程進行方式 : 投影片教學(Projector) 課程講義: 影印發放 + 自行購買
作業部份:期中報告/期末報告。 考試部份: 期中考試/期末考試 依照學校規定時程舉行。 評量部份:學期成績 = (期中考試×20%) + (期末考試×20%) + (作業/報告成績×60%)。 註:以上配分比例,會依群體學習績效酌與調整,由授課教授最後決定之。
- [1] Introduction to ESD (Electrostatic Discharge) [2] Industrial Standards on ESD Events [3] ESD Testing on ICs [4] Transmission-Line Pulse Generator (TLP) [5] Process Issues on ESD Robustness of CMOS ICs [6] Device Issues on ESD Robustness of CMOS ICs [7] Layout Issues on ESD Robustness of CMOS ICs [8] Design of on-chip ESD Protection Circuits [9] Whole-Chip ESD Protection Scheme [10] ESD Protection Design for RF Circuits [11] ESD Protection Design for Mixed-Voltage I/O Circuits [12] ESD Protection in High-Voltage CMOS ICs [13] System-Level ESD Protection [14] Latchup Prevention in CMOS ICs [15] I/O Cell Library with ESD Protection Design [16] Cases Study and Failure Analysis
| 週次 | 主題 |
|---|---|
| 第 1 週 | [1] Introduction to ESD (Electrostatic Discharge) [2] Industrial Standards on ESD Events |
| 第 2 週 | [3] ESD Testing on ICs [4] Transmission-Line Pulse Generator (TLP) |
| 第 3 週 | [5] Process Issues on ESD Robustness of CMOS ICs |
| 第 4 週 | [6] Device Issues on ESD Robustness of CMOS ICs |
| 第 5 週 | [7] Layout Issues on ESD Robustness of CMOS ICs |
| 第 6 週 | [8] Design of on-chip ESD Protection Circuits |
| 第 7 週 | [9] Whole-Chip ESD Protection Scheme |
| 第 8 週 | [9] Whole-Chip ESD Protection Scheme |
| 第 9 週 | [10] ESD Protection Design for RF Circuits |
| 第 10 週 | [11] ESD Protection Design for Mixed-Voltage I/O Circuits |
| 第 11 週 | [12] ESD Protection in High-Voltage CMOS ICs |
| 第 12 週 | [13] System-Level ESD Protection |
| 第 13 週 | [14] Latchup Prevention in CMOS ICs |
| 第 14 週 | [14] Latchup Prevention in CMOS ICs |
| 第 15 週 | [15] I/O Cell Library with ESD Protection Design [16] Cases Study and Failure Analysis |
| 第 16 週 | 期末考 |
本課程由授課教師自行編輯專家等級之授課講義資料,無指定之教科書。 直接相關之參考書目,如下所列,有興趣者請自行參閱。 參考書目: 1. A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, John Wiley & Sons, 2nd Edition, 2002. (TI) 2. S. Voldman, ESD : Circuits and Devices, John Wiley & Sons, 2006. (IBM) 3. S. Voldman, ESD : RF Technology and Circuits, John Wiley & Sons, 2006. (IBM) 4. S. Dabral and T. Maloney, Basic ESD and I/O Design, John Wiley & Sons, 1988. (Intel) 5. S. Voldman, ESD : Physics and Devices, John Wiley & Sons, 2004. (IBM) 6. A. Wang, On-Chip ESD Protection for Integrated Circuits, Kluwer, 2002. (AMD) 7. M.-D. Ker and S.-F. Hsu, Transient-Induced Latchup in CMOS Integrated Circuits, John Wiley & Sons, 2009. (NCTU, Taiwan) 8. S. Voldman, Latchup. Hoboken, NJ: Wiley, 2007. 9. V. A. Vashchenko and A. Shibkov, ESD Design for Analog Circuits, Springer, 2010. (Maxim) 10. O. Semenov, H. Sarbishaei, and M. Sachdev, ESD Protection Device and Circuit Design for Advanced CMOS Technologies, Springer, 2010. (Univ. of Waterloo) 11. Electrostatic Discharge Protection: Advances and Applications, edited by Juin J. Liou, CRC Press, 2016. (ISBN : 978-1482255881 ) 12. Papers in the International Journals and Transactions. 13. Papers in the Proceedings of International Conferences. 14. Papers in the Proceedings of EOS/ESD Symposium. 15. International Standards. 16. US Patents.
- 地點
- ED-307
- 時間
- PM 4:00 - 5:30, Monday.
- 聯絡方式
- 助教: 柯兆陽 [ cyke@nycu.edu.tw ]