校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15/2026
  • 初選第二階段 6/22/2026
  • 校際選修 8/24/2026
  • 初選第三階段 8/31/2026
  • 開學後加退選 9/7/2026
  • 逾期加退選 9/21/2026
選課資源

類比混合訊號電路設計特論

Special topics in analog mixed-signal circuit design

學期
113-1
學分
3 學分
當期課號
539002
永久課號
IIPS30001
開課單位
前瞻半導體研究所
授課教師
蕭振宇、許雲翔
校區
光復
類別
選修
上課時間表
週五
6
14:20–15:10
類比混合訊號電路設計特論
EC015
3 節連堂
7
15:30–16:20
8
16:30–17:20

* 根據陽明交大上課時間表所列

概述

This course will introduce the fundamentals of various ADC/Wireline architectures. The content will cover the building blocks of ADC/Wireline and their non-idealities in practical circuits. Students will need to select one of the ADC/Wireline architectures and practice the design flow, starting from Matlab modeling and circuit simulation with ideal blocks, and then progressing to replacing parts of the blocks with real circuits.

先修科目

Microelectronics, Circuit theories, Introduction to analog integrated circuits

教學方式

Reference : 1. Behzad Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, 1994. 2. Phillip E. Allen, Douglas R. Holberg, “CMOS Analog Circuit Design,” OXFORD, 2012, 3rd-Edition

評分方式

Midterm exam 15%, Final exam 15%, Homework 40%, Final project 30%

週次計畫
週次主題
第 1 週Introduction of this Course (content & rating rules) Overview of ADC Architectures
第 2 週ADC Performance Indexes and Flash ADC
第 3 週Comparator and SAR ADC
第 4 週Oversampling and Noise Shaping
第 5 週Delta-Sigma Modulator
第 6 週Pipelined ADC and Digital Calibration
第 7 週Midterm Examination (ADC)
第 8 週High-Speed Links Overview -SerDes standards and link sequence -Noise and signaling
第 9 週High-Speed Links Circuits and Systems -Receiver circuits: AFE, DFE, adaptive algorithm
第 10 週High-Speed Links Circuits and Systems -Receiver circuits: CDR, De-Multiplexer
第 11 週High-Speed Links Circuits and Systems -Transmitter circuits: Driver, Multiplexer, FIR EQ
第 12 週Phase-Locked Loop (PLL) -Introduction of PLL -Building Blocks in PLL
第 13 週Phase-Locked Loop (PLL) -Phase noise and jitter -PLL Implementation and Simulation
第 14 週Final Project Report (ADC)
第 15 週Final Project Report (High-Speed Links/PLL)
第 16 週Final Examination (High-Speed Links/PLL)
教科書

Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001.