機器學習智能晶片設計
Machine Learning Intelligent Chip Design
| 節 | 週三 |
|---|---|
2 09:00–09:50 | 機器學習智能晶片設計 ED219 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
機器學習晶片在近年來被廣泛的應用於各式邊緣運算的應用中,機器學習晶片屬於多核心系統晶片設計的一個分支,本課程使用SystemC語言讓學生了解一個多核心系統晶片設計架構的評估與運作方式。首先將介紹機器學習晶片的設計概論,接著介紹脈動陣列(systolic array)以及晶片內網路架構。最後,本課程也將介紹多核心系統晶片的架構以及運作流程,使學生能了解一個機器學習系統晶片設計的完整運作方式,並有能力透過SytemC語言來實現。 The machine learning chip has been widely applied to various applications of edge computing in recent years. It is a branch of the multi-processor system on chip (MPSoC). This course will enable students to use SystemC to understand and evaluate the operational mechanisms of MPSoC. Initially, the course will cover the fundamentals of machine learning chip design methods. Following this, it will introduce the systolic array architecture and the Network-on-Chip (NoC) architecture. Finally, the course will explore MPSoC architecture and its operational flow, with the goal of helping students comprehend the complete operational mechanism of Machine Learning MPSoC and implement it using SystemC.
計算機組織/結構 (Computer Organization/Architecture)、計算機程式 (Computer Programming)
1. 本門課因空間因素,不接受手動加簽,請直接在線上選課,不接受超過上限人數。上限人數有可能因空間關係隨時做調整。請自行注意。 2. 部分課程會採用錄影方式進行,請按公告至E3上觀看。 3. 本課程部份週數為上機課程,請按公告進行。 4. 本課程鼓勵討論,但嚴禁抄襲,抄襲與被抄襲者當次作業/考試皆為0分。 1. Due to space constraints, manual add-ons are not accepted for this course. Please directly enroll online and note that exceeding the maximum number of participants is not allowed. The maximum limit may be adjusted based on the space constraints. 2. Some courses will be conducted through recorded video. Please refer to the announcements and watch on E3. 3. Some weeks, classes will switch to lab classes. Please follow the announcements for further instructions. 4. This course encourages discussion but strictly prohibits plagiarism. Both the plagiarizer and the victim of plagiarism will receive a score of zero for the respective assignment/exam.
Homework: 10% Lab: 10% Final project: 30% Midterm Exam: 25% Final Exam: 25%
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction and syllabus |
| 第 2 週 | SystemC overview and data type |
| 第 3 週 | SystemC: Module description |
| 第 4 週 | (Lab) SystemC: Exercise |
| 第 5 週 | SystemC: Interface and channel |
| 第 6 週 | Fundamental of DNN Accelerator Design |
| 第 7 週 | Spring Break NYCU Sports Day |
| 第 8 週 | Midterm Exam |
| 第 9 週 | Systolic architecture design |
| 第 10 週 | Introduction to Network on Chip – (1) |
| 第 11 週 | Introduction to Network on Chip – (2) |
| 第 12 週 | (Lab) SystemC: Exercise |
| 第 13 週 | 1. SoC overview and on-chip protocol 2. Interface |
| 第 14 週 | (Lab) SystemC: Exercise |
| 第 15 週 | Interface |
| 第 16 週 | Final Exam |
| 第 17 週 | |
| 第 18 週 |
1. Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, and Joel S. Emer, Efficient Processing of Deep Neural Networks, , Morgan & Claypool, 2020. 2. David C. Black, Jack Donovan, Bill Bunton, and Anna Keist, SystemC: From the Ground Up, Springer, 2010. 3. Natalie E. Jerger and L.-S. Peh, On-Chip Networks, Morgan & Claypool, 2009.
- 地點
- ED404
- 時間
- 10 am – 12 pm, Monday
- 聯絡方式
- kcchen@nycu.edu.tw