進行中 校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15 – 6/18
  • 初選第二階段 6/22 – 6/25
  • 校際選修 8/24 – 9/18
  • 初選第三階段 8/31 – 9/3
  • 開學後加退選 9/7 – 9/21
  • 逾期加退選 9/21 – 9/24
選課資源

進階可程式邏輯系統設計與應用

Advanced Programmable Logic System Design and Application

學期
113-2
學分
3 學分
當期課號
535309
永久課號
EECN30203
開課單位
電控工程研究所
授課教師
歐陽盟
校區
光復
類別
選修
上課時間表
週三
7
15:30–16:20
進階可程式邏輯系統設計與應用
EE634
2 節連堂
8
16:30–17:20
A
18:30–19:20
進階可程式邏輯系統設計與應用
EE634
3 節連堂
B
19:30–20:20
C
20:30–21:20

* 根據陽明交大上課時間表所列

概述

This course is teaching students with or without the basic FPGA knowledge to accomplish a digital system for control, communication, bioelectrical and other applications. Students must design a special project using FPGA, ARM, uProcessor or combinations to design an unique task. All arts will be encouraged to attend the international FPGA technology competition.

先修科目

Logic Design or Digital System

教學方式

(1) 2-hr lecture and 3-hr lab. course every week. The PPT file and experiment will both be adopted for the explanation of the content in the textbook. (2) In order to respect the Intelligent Property of the Textbook, the PPT file could not be provided, and purchasing the textbook is encouraged. All the material, including material on the course, homework, and projects, will be sourced from the textbook, which would have been authorized by the book publisher and authors. (3)期末需有專題發表

評分方式

(1) 10 Experiments: (10X10)X0.4=40% (2) Midterm Exam. (on-site) : 20% (3) Final Exam. (on-site) : 20 % (4) Final Project : 20%

週次計畫
週次主題
第 1 週
第 2 週
第 3 週
第 4 週
第 5 週
第 6 週
第 7 週
第 8 週
第 9 週
第 10 週
第 11 週
第 12 週
第 13 週
第 14 週
第 15 週
第 16 週
教科書

[1] Stephen Brown and Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design,” 3rd. Edition, McGraw-Hill, 2014. [2] Terasic Tech., “Development Kits,” 2014.

Office Hours
地點
EE740 EE814
時間
(1) Mon. 0900-2100 : 歐陽盟, EE740, ext.54416, oym@nycu.edu.tw (2) Mon. 0900-2100 : Dr. 顏永哲, EE814, ext.54415, jerryyan@nycu.edu.tw (3) 相關問題可email給老師,並請副本給邱盈淑助理,lobby8612@nycu.edu.tw,ext.54343。
聯絡方式
ext.54416 ext.54415