VLSI 導線效應之模型與最佳化

Present a broad survey of the problems in modeling and design of high-performance VLSI interconnect and state of art solutions. Provide necessary background for graduate students to carry out research in this area.

Mainly self-contained

Course Website: http://vlsi-eda.cm.nctu.edu.tw/course/Interconnect_15Spring/home.html TA: Hung-Wen Chiou Office: ED718 E-mail: simon00195@yahoo.com.tw Phone: 54586

1) Homework/Quiz/Midterm/Final: 40% 2) Paper Survey: 30% 3) Project: 30%

• Overview and Introduction
• Modeling of VLSI Interconnects
• Introduction to Parasitic Extraction
• Interconnect Delay Modeling & Calculation
• Interconnect Sizing
• Introduction of Noise Modeling and Reduction
• Power Delivery Network Analysis and Design
• Thermal Issues, Modeling and Analysis
• Introduction to Clock Network Design

1) C. K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis and Synthesis, John Wiley & Sons, Inc. 2000. 2) Ashok K. Goel, High-Speed VLSI Interconnects, second edition, John Wiley & Sons, Inc. 2007. 3) Cong et al., Performance Optimization of VLSI Interconnect Layout, Integration, the VLSI Journal 21, 1996 1--94. 4) M. Celik, L. Pileggi, A. Odabasioglu, IC Interconnect Analysis, Kluwer Academic Publishers, 2002. 5) J. M. Rabaey, A. Chandrakasan, B. Nikolić, Digital Integrated Circuits A Design Perspective, Pearson Education, Inc. 2003 6) N. Menezes, L. Pileggi, Analyzing On-chip Interconnect Effects, Chapter 16 in Design of High-Performance Microprocessor Circuits, IEEE Press, 2001. 7) H. B. Bakoglu, Circuits, Interconnects, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990. 8) Sheldon C. D. Tan, L. He, Advanced Model Order Reduction Techniques in VLSI Design, Cambridge University Press 2007. 9) Selected research papers from IEEE TCAD, ACM TODAES, and major CAD conference such as DAC, ICCAD, ISPD, and DATE.

地點

ED835

時間

11:00~12:00 Tuesday or by appointment

聯絡方式

E-mail: yumin@nctu.edu.tw Phone: 31274