邏輯設計
Logic Design
| 節 | 週二 | 週五 |
|---|---|---|
3 10:10–11:00 | 邏輯設計 EE220 2 節連堂 | |
4 11:10–12:00 | ||
5 13:20–14:10 | 邏輯設計 EE220 |
* 根據陽明交大上課時間表所列
This course enables students to acquire a fundamental understanding of digital systems and binary logic operations, master number systems and Boolean algebra, analyze and design digital circuits, and design combinational and sequential logic systems. Students will also develop problem-solving and abstraction skills. Therefore, upon completing this course, students will be able to apply digital logic in related professional fields in the future. 本課程旨在幫助學生掌握數位系統和二元邏輯運算的基礎知識,掌握數係和布林代數,分析和設計數位電路,以及設計組合邏輯和時序邏輯系統。學生還將培養解決問題和抽象思維的能力。因此,在完成本課程後,學生將能夠在未來的相關專業領域中運用數位邏輯。
Students shall have essential capability of English reading. 學生應具備基本的英語閱讀能力。
Lecture with power point file E3 on line system
Homeworks and Quizs 25% Extra credits (mini-project) and attendance rate 15% Midterm Examination 30% Final Examination 30%
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1. Number System and Conversion |
| 第 2 週 | 2. Boolean Algebra |
| 第 3 週 | 3. Algebraic Simplification |
| 第 4 週 | 4. Applications of Boolean Algebra |
| 第 5 週 | 5. Karnaugh Maps |
| 第 6 週 | 6. Multi-Level Gate Networks NAND and NOR Gates |
| 第 7 週 | 7. Multi-Level Gate Networks NAND and NOR Gates |
| 第 8 週 | 8. Midterm examination |
| 第 9 週 | 9. Combinational Circuits Design and Simulation Using Gates |
| 第 10 週 | 10. Multiplexers, Decoders, Read-Only Memories, and Programmable Logic Devices |
| 第 11 週 | 11. Latches and Flip-Flops |
| 第 12 週 | 12. Registers and Counters |
| 第 13 週 | 13. Analysis of Clocked Sequential Circuits |
| 第 14 週 | 14. Reduction Derivation of State Graphs and Tables |
| 第 15 週 | 15. Reduction of State Tables/State Assignment |
| 第 16 週 | 16. Sequential Circuit Design |
| 第 17 週 | 17. Final Exam |
Fundamentals of Logic Design Enhanced 7/e, Charles H. Roth, Jr. and Larry L. Kinney
- 地點
- ED528-6
- 時間
- Friday 12:30-13:30
- 聯絡方式
- By email: speng@nycu.edu.tw