鎖相迴路與頻率合成
Phase locked loop and Frequency Synthesizer
| 節 | 週一 |
|---|---|
6 14:20–15:10 | 鎖相迴路與頻率合成 EDB01 3 節連堂 |
7 15:30–16:20 | |
8 16:30–17:20 |
* 根據陽明交大上課時間表所列
1. Introduction ( ref: Wolaver Chap1, Best Chap1) a) Category of PLL b) Applications of PLL in Modern Receivers. 2. PLL Modeling and Dynamics (ref: Wolaver Chap2 and 3, Blanchard chap. 1-3, and Smith Chap9) a) PLL Static and DC Offset b) PLL Type, Order, and Stability c) Transient Analysis d) Steady state error e) Synthesizer Design Example (ref: Motorola AN535) f) Measurement of PLL Parameters(ref: R. Best, chap.7) 3. Phase Noise in PLL (ref. Wolaver Chap. 6, Simth Chap. 10, and Rohde Chap. 2) 4. Frequency Synthesizer and Fractional N Synthesizer Integer N Synthesizer Synthesizer for Communication Sigma-Delta Scheme 5. Oscillators LC Cross-Coupled VCO Meyhods for Quadratic Phase Generator Ring Oscillator Crystal Oscillators 6. Digital Circuits in PLL Phase Detectors(Ref: Wolaver Chap. 4, Razavi Chap. 8) Ex-OR, Two-State, and Three State, Charger Pump Prescaler Programmable Divider
分數 1. 期中考一次 30% 2. 課堂作業 70%
| 週次 | 主題 |
|---|---|
| 第 1 週 | chap 1 |
| 第 2 週 | chap 2 |
| 第 3 週 | chap 1 |
| 第 4 週 | chap 2 |
| 第 5 週 | chap 2 |
| 第 6 週 | chap 3 |
| 第 7 週 | chap 3 |
| 第 8 週 | chap 3 |
| 第 9 週 | chap 3 |
| 第 10 週 | mid term exam |
| 第 11 週 | chap 4 |
| 第 12 週 | chap 4 |
| 第 13 週 | chap 4 |
| 第 14 週 | chap 5 |
| 第 15 週 | chap 5 |
| 第 16 週 | chap 5 |
| 第 17 週 | Final report |
| 第 18 週 | Final Report |