校際選修

115-1 選課時程

進行中

  • 初選第一階段 6/15/2026
  • 初選第二階段 6/22/2026
  • 校際選修 8/24/2026
  • 初選第三階段 8/31/2026
  • 開學後加退選 9/7/2026
  • 逾期加退選 9/21/2026
選課資源

數位實驗

Digital Laboratory

學期
114-2
學分
3 學分
當期課號
515108
永久課號
EEEC10005
開課單位
電機工程學系
授課教師
陳建安
類別
選修
上課時間表
週四
A
18:30–19:20
數位實驗
4 節連堂
B
19:30–20:20
C
20:30–21:20
D
21:30–22:20

* 根據陽明交大上課時間表所列

概述

本課程 FPGA 開發須使用 AMD Vivado 軟體,修課同學須自備足以順利執行的電腦參與課程。(軟體官方需求說明 https://www.amd.com/en/support/adaptive-socs-and-fpgas/installer-info-general.html) 一、利用「開關」、「電晶體」、「FPGA」等元件,實踐邏輯設計中的電路,例如:基本邏輯閘(AND、OR、NOT、XOR、NAND、NOR)、正反器(SR Latch、Flip-Flop)、組合邏輯、序向邏輯、有限狀態機等。 二、練習使用與電子電路相關的測量儀器,例如:電源(power supply)、示波器(oscilloscope)、邏輯分析儀(logic analyzer)、數位訊號產生器(pattern generator)。 三、利用「邏輯設計」概念,設計並實現大型電路於 FPGA 平台。 四、練習撰寫實驗報告,包含:實驗目的、觀察數據、步驟描述、現象描述、結果分析、除錯過程、設計方法等。 五、練習自行查找資料(網路或書籍),並自行尋找可幫助開發的工具與設計模式。 六、練習團隊開發,藉由期末專題製作過程,合理分配工作與有效實現大型專案。 This course requires the use of "AMD Vivado" software for FPGA development. Students enrolled in the course must bring their own computers capable of running the software smoothly to participate. (Please refer to the "official software system requirements": https://www.amd.com/en/support/adaptive-socs-and-fpgas/installer-info-general.html) 1. Use components such as switches, transistors, and FPGAs to implement circuits in logic design, including basic logic gates (AND, OR, NOT, XOR, NAND, NOR), latches and flip-flops (SR latch, flip-flop), combinational logic, sequential logic, finite state machines, and related circuits. 2. Practice using measurement instruments related to electronic circuits, such as power supplies, oscilloscopes, logic analyzers, and digital signal/pattern generators. 3. Apply logic design concepts to design and implement large-scale circuits on the FPGA platform. 4. Practice writing laboratory reports, including: experiment objectives, observed data, procedural descriptions, observed phenomena, result analysis, debugging processes, and design methodologies. 5. Practice independent information retrieval (from online resources or books) and identifying tools and design patterns that support development. 6. Practice team-based development by reasonably allocating tasks and effectively implementing a large project through the final course project.

先修科目

已修畢或正在修邏輯設計課程者 Course Site: https://sites.google.com/nycu.edu.tw/nycueelabs/digital 實驗課內容份量多,需要花很多時間。請選課同學謹慎考慮。 學期第一週(準備週)現場處理加退選,同學須本人簽到。 Students who have completed or are currently taking the Logic Design course. Course Site: https://sites.google.com/nycu.edu.tw/nycueelabs/digital The laboratory course has a heavy workload and requires a significant time commitment. Students are advised to carefully consider this before enrolling. Add/drop procedures will be handled in person during the first week of the semester (preparation week), and students must sign in personally.

教學方式

課程網站:https://sites.google.com/nycu.edu.tw/nycueelabs/digital

評分方式

欲選修「數位實驗」課程的同學,請先閱覽下面資源. Students who wish to enroll in the Digital Laboratory course, please first review the resources below. -影片觀賞1:https://youtube.com/playlist?list=PL8dPuuaLjXtNlUrzyH5r6jN9ulIgZBpdo -影片觀賞2:https://youtube.com/playlist?list=PLSTiCUiN_BoLtf_bWtNzhb3VUP-KDvv91 -語法教學文件:https://www.google.com/url?q=https%3A%2F%2Fwww.chipverify.com%2Fverilog%2Fverilog-tutorial&sa=D&sntz=1&usg=AOvVaw19Ruxq8-e1mTKWYvcIdJir Quiz (可能有1~4次) 實驗驗收 Demo 實驗結報 Lab Report 專題驗收 Project Demo 專題結報 Project Report

週次計畫
週次主題
第 1 週準備週 (現場處理加退選,須本人到場)
第 2 週Lab01: Switch circuit and basic AD2 function
第 3 週Lab02: Transistor-level / IC-level logic gate implementation
第 4 週Lab03: Gated SR latch and 74191 counter IC
第 5 週Lab04: 74 series IC & 7-segments display
第 6 週校際活動週(放假)
第 7 週FPGA Live Course (無驗收項目,同學須簽到) (領用 FPGA 設備) (現場授課,同學須帶電腦至實驗室)
第 8 週課程期中考試(10日-14日) 停課一次
第 9 週Lab05: FPGA Experiments part1
第 10 週Lab06: FPGA Experiments part2
第 11 週Lab07: FPGA Experiments part3
第 12 週Lab08: FPGA Experiments part4
第 13 週Final Project Implementation Start
第 14 週Class suspend-Final Project Implementation
第 15 週Final Project Live Demo
第 16 週Return all materials and devices
教科書

自行編撰教材 Self-developed instructional materials https://sites.google.com/nycu.edu.tw/nycueelabs/fpga-development-and-xilinx-vivado

Office Hours
地點
ED313 辦公室 (或 ED222)
時間
來信預約
聯絡方式
ccata@nycu.edu.tw