數位電路與系統
Digital Circuits and Systems
| 節 | 週二 | 週四 |
|---|---|---|
7 15:30–16:20 | 數位電路與系統 ED713 2 節連堂 | |
8 16:30–17:20 | 數位電路與系統 ED713 2 節連堂 | |
9 17:30–18:20 |
* 根據陽明交大上課時間表所列
本課程將介紹IC設計的前段設計流程以及系統架構設計的基本概念，首先讓學生了解如何使用Verilog-HDL來進行可合成電路的設計與驗證，接者本課程將介紹幾種電路設計優化的方法，並介紹如何透評估電路設計的優劣。最後，本課程將介紹系統晶片的基本架構與運作機制，並使用FPGA來讓學生了解實際系統晶片的運作流程。課程當中會介紹IC設計前段流程中所使用的常見電腦輔助設計(CAD)工具，並且介紹如何透過面積-時間-功耗分析、程式設計方法等技巧來設計一個有效的數位電路與系統。 This course provides an introduction to the front-end digital IC design flow and the basics of system architecture design. It begins with synthesizable circuit design and verification using Verilog-HDL. Students will then learn various design strategies for optimizing circuit design and methods for evaluating circuit performance. The course will also cover the fundamentals of System on Chip (SoC) architecture and its operational mechanisms. Additionally, students will gain hands-on experience with a real SoC operation flow through practical exercises in FPGA design. The course will address commonly used Computer-Aided Design (CAD) tools in the front-end digital IC design process and emphasize how to create effective digital circuits and systems by focusing on ATP (Area-Timing-Power) analysis and best coding practices.
邏輯設計 logic design
1. 本門課因空間因素，不接受超過上限人數的加簽。上限人數有可能因空間關係隨時做調整。請自行注意。 2. 部分課程會採用錄影方式進行，請按公告至E3上觀看。 3. 第三周起的每周四下午為上機課程，請按公告進行。 4. 本課程鼓勵討論，但嚴禁抄襲，抄襲與被抄襲者當次作業/考試皆為0分。 1. Due to space constraints, manual add-ons are not accepted for this course. Please directly enroll online and note that exceeding the maximum number of participants is not allowed. The maximum limit may be adjusted based on the space constraints. 2. Some courses will be conducted through recorded video. Please refer to the announcements and watch on E3. 3. Starting from the third week, Thursday afternoons will switch to Lab class. Please follow the announcements for further instructions. 4. This course encourages discussion but strictly prohibits plagiarism. Both the plagiarizer and the victim of plagiarism will receive a score of zero for the respective assignment/exam.
Homework (25%)/ Lab (10%) 35% Final project 25% Midterm exam 15% Final exam 25% (including online test)
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction and syllabus |
| 第 2 週 | Verilog Overview |
| 第 3 週 | Register-Transfer Level (RTL) |
| 第 4 週 | Logic Design at Behavioral Level |
| 第 5 週 | Testbench |
| 第 6 週 | 3/31 Synthesizable Verilog Coding 4/2 Holiday |
| 第 7 週 | Static Timing Analysis (STA) |
| 第 8 週 | Midterm Exam |
| 第 9 週 | Pipelining and Parallel Processing |
| 第 10 週 | SoC overview |
| 第 11 週 | On-chip communication protocol |
| 第 12 週 | 1. On-chip communication protocol 2. Folding and unfolding |
| 第 13 週 | Folding and unfolding |
| 第 14 週 | FPGA Verification |
| 第 15 週 | Final exam |
| 第 16 週 | Online test |
1. M. Morris R. Mano and Michael D. Ciletti, Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog 6th edition, Pearson, 2019 (ISBN: 978-1-292-23116-7) 2. Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley, 1999 (ISBN: 978-8-126-51098-6)
- 地點
- ED414
- 時間
- 10 am - 12 pm, Monday
- 聯絡方式
- kcchen@nycu.edu.tw