超大型積體電路設計導論
Introduction to VLSI Design
| 節 | 週四 |
|---|---|
5 13:20–14:10 | 超大型積體電路設計導論 ED101 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
This course aims to convey junior EE students techniques to analyze and design system by means of VLSI technology and CAD tools. Starting from VLSI process technology and transistor's behavior. an indepth discussion covering circuit, logic, and subsystem designs will be presented. Upon completion of the course, the student will be able to design system-level IC (SLIC) based on available VLSI technology and CAD tools. As such he/she will be able to work in a team of designers or stand alone to meet system-level specifications. The course offers a complete yet accessible introduction to crosstalk models and optimization. It covers minimizing power consumption at every level of abstraction, from circuits to architecture and new insights into design-for-testability (DFT) techniques that maximize quality despite quicker turnarounds. It also presents detailed coverage of the algorithms underlying contemporary VLSI computer-aided design (CAD) software, so designers can understand their tools no matter which ones they choose. This course mainly contains 4 topics which are essential to the practice of VLSI design as a system design discipline. They are given below and will be addressed in more detail during lecture and discussion. 1. Transistor modeling and physical design constraints 2. Basic circuit and logic designs 3. Data path and sub-system designs 4. Design methodology for architecture optimization, testing and low-power
logic design, Electronics (I)
Students who want to take this course are required to attend the first class. If the number of applicants exceeds the available spots, a lottery system will be used to determine the final enrollment. TA: 1. 余家佑 Jia-You Yu (lorenzpremium1016@gmail.com) 2. 梁文熏 Wen-Hsun Liang (tippi.ii14@nycu.edu.tw)
Midterm Exam: 20% Final Exam: 20% In-Class Quiz: 20% Midterm Project: 15% Final Project: 25%
| 週次 | 主題 |
|---|---|
| 第 1 週 | |
| 第 2 週 | Introduction to VLSI |
| 第 3 週 | Circuits and Layout |
| 第 4 週 | Circuits Transistor Theory |
| 第 5 週 | Logical Effort |
| 第 6 週 | No Class |
| 第 7 週 | Combinational Circuits |
| 第 8 週 | Midterm Exam Midterm Project |
| 第 9 週 | Sequential Circuits |
| 第 10 週 | Adders |
| 第 11 週 | Datapath and Arithmetic Operators |
| 第 12 週 | Datapath and Arithmetic Operators |
| 第 13 週 | SRAM |
| 第 14 週 | Design Methodology and CAD |
| 第 15 週 | Optimizing Power at Design Time |
| 第 16 週 | Final Exam Final Project |
| 第 17 週 | Final Project |
| 第 18 週 | Final Project |
"CMOS VLSI Design—A circuits and systems Perspective" by Neil H.E. Weste and David Harris. (3rd Edition from Addison Wesley, ISBN:0-321-26977-2)
- 地點
- ED403
- 時間
- Friday from 08:00-09:00 (Booking via Email)
- 聯絡方式
- email: yicwu@ncyu.edu.tw