邏輯設計【英文班】
Logic Design
學期
114-2
學分
3
學分
當期課號
515159
永久課號
EEEC10025
開課單位
電機工程學系
授課教師
粘儆夫
校區
光復
類別
必修
上課時間表
| 節 | 週三 |
|---|---|
N 12:20–13:10 | 邏輯設計【英文班】 ED202 3 節連堂 |
5 13:20–14:10 | |
6 14:20–15:10 |
* 根據陽明交大上課時間表所列
概述
This course introduces the fundamentals of digital systems and logic design. Students will learn number systems, Boolean algebra, and methods for simplifying logic expressions. The course covers both combinational and sequential circuits, including multiplexers, decoders, latches, flip-flops, counters, and state machines. The goal is to prepare students for advanced courses in digital design, computer architecture, and design automation.
先修科目
NONE
教學方式
Lecture with PowerPoint slides
評分方式
Midterm Exam: 30% Homework and Quizzes: 20% Final Exam: 30% Course Attendance: 10%
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | Course Introduction / Number Systems and Conversion |
| 第 2 週 | Boolean Algebra |
| 第 3 週 | Algebraic Simplification |
| 第 4 週 | Applications of Boolean Algebra |
| 第 5 週 | Karnaugh Maps |
| 第 6 週 | Multi-Level Gate Networks: NAND and NOR Gates |
| 第 7 週 | Combinational Circuit Design and Simulation Using Gates |
| 第 8 週 | Exam 1 |
| 第 9 週 | Multiplexers, Decoders, and Programmable Logic Devices |
| 第 10 週 | Latches and Flip-Flops |
| 第 11 週 | Registers and Counters |
| 第 12 週 | Analysis of Clocked Sequential Circuits |
| 第 13 週 | Derivation of State Graphs and Tables |
| 第 14 週 | Reduction of State Tables / State Assignment |
| 第 15 週 | Sequential Circuit Design |
| 第 16 週 | Exam 2 |
教科書
Roth Jr. and L. Kinney, Fundamentals of Logic Design, 7th edition, Cengage, 2014.
Office Hours
- 地點
- Instructor's office (ED 528-1)
- 時間
- By appointment
- 聯絡方式
- Schedule can be made in person or through e-mail (watchmannien@nycu.edu.tw)