程式化邏輯系統設計

This course is teaching students the techniques on large scale logic design and familiarizing them with FPGA platform. Students will learn the use of VHDL or Verilog and digital system prototyping and simulation.

Logic Design or Digital System

(1) 2-hr lecture and 3-hr lab. course every week. The PPT file and experiment both will be adopted for the explanation of the content in the textbook. (2) In order to respect the Intelligent Property of the Textbook, the PPT file could not be provided, and purchasing the textbook is encouraged. All the material including material on the course, homework, and project will be sourced from the textbook which would have been authorized by the book publisher and authors. (3) Teaching Assistant info.: 顏永哲, EE814, ext.54415, yanjohn888@gmail.com

(a) ten experiments (b) one midterm examination and one final examination Evaluation： Experiment: 10 X 10 X 50%=50 points Midterm: 100 X 20% = 25 points Final: 100 X 25% = 25 points

S. Brown and Z. Vranesic, “Fundamentals of Digital Logic with Verilog Design,” 3rd Edition, McGraw-Hill

地點

EE740 EE814

時間

(1) Tue. 0900-2200 : 歐陽盟; oym@nycu.edu.tw (2) Tue. 0900-2200 : 顏永哲; yanjohn888@gmail.com

聯絡方式

ext.54416 ext.54415