數位電路設計
Digital Circuit Design
學期
114-2
學分
3
學分
當期課號
515503
永久課號
CSCS10005
開課單位
資訊學院共同課程
授課教師
范倫達
校區
光復
類別
必修
上課時間表
| 節 | 週三 | 週五 |
|---|---|---|
3 10:10–11:00 | 數位電路設計 ED117 2 節連堂 | |
4 11:10–12:00 | ||
7 15:30–16:20 | 數位電路設計 ED117 |
* 根據陽明交大上課時間表所列
概述
This course is aimed at introducing and demonstrating the fundamental logic design concepts for digital systems.
先修科目
Not needed.
教學方式
http://viplab.cs.nycu.edu.tw/course/DCD2025_Spring.php
評分方式
Grading Policy: 1) Quizzes 2) Examinations 3) Participation
課程大綱
- Digital Systems and Binary Numbers
- Boolean Algebra and Logic Gates
- Gate-Level Minimization
- Combinational Logic
- Synchronous Sequential Logic
- Register and Counters
- Memory and Programmable Logic
週次計畫
| 週次 | 主題 |
|---|---|
| 第 1 週 | 1. Digital Systems 2. Binary Numbers |
| 第 2 週 | 1. Number-Base Conversion 2. Binary Logic |
| 第 3 週 | 1. Basic Theorems and Properties of Boolean Algebra 2. Boolean Functions 3. Canonical and Standard Forms 4. Digital Logic Gates |
| 第 4 週 | 1. The K-Map Method 2. Product of Sums Simplification |
| 第 5 週 | 1. Don't-Care Conditions 2. NAND and NOR Implementation 3. Other Two-level Implementation |
| 第 6 週 | 1. Combinational Circuits 2. Design Procedure |
| 第 7 週 | 1. Binary Adder-Subtractor/Decimal Adder 2. Binary Multiplier 3. Decoder/Encoder/Multiplexer |
| 第 8 週 | 1. Latches 2. Flip-Flops |
| 第 9 週 | 1. State Reduction and Assignment 2. Design Procedure |
| 第 10 週 | Midterm |
| 第 11 週 | 1. Registers 2. Shift Register |
| 第 12 週 | 1. Ripple Counter 2. Synchronous Counter |
| 第 13 週 | 1. RAM 2. Memory Decoding 3. Error Detection and Correction |
| 第 14 週 | 1. ROM 2. Programmable Logic Array 3. Programmable Array Logic |
| 第 15 週 | Content Review |
| 第 16 週 | Final Exam |
教科書
Text Book: M. Morris Mano and Michael D. Ciletti, "Digital Design", 6th Ed, Prentice Hall, 2019.
Office Hours
- 地點
- EC419R
- 時間
- Wednesday 8AM~10AM
- 聯絡方式
- 5712121-54815