記憶體積體電路

(Chinese) 本課程旨在透過「專題導向學習（PBL）」結合「業界標準設計流程」，解決記憶體積體電路課程中理論與實務脫節之痛點。教學目標聚焦於三層次之能力養成：首先在實務技能層面，學生須運用專業EDA工具，獨立完成從SRAM單元、感測放大器至1k-bit記憶體陣列的完整設計，涵蓋電路圖、佈局（Layout）及後模擬（Post-Sim），並掌握靜態雜訊邊際（SNM）與製程變異分析。其次在工程思維層面，培養學生具備PPA（效能、功耗、面積）之設計權衡（Trade-off）能力，從被動操作轉為主動邏輯除錯。最終目標為提升就業競爭力，協助學生產出符合產業規範的晶片設計作品集，有效縮短學用落差。 (English) This course aims to bridge the gap between theory and practice in Memory IC education by combining Project-Based Learning (PBL) with industry-standard design flows. The instructional objectives focus on cultivating competencies across three levels: a. Practical Skills: Students will use professional EDA tools to independently complete a full design cycle—from SRAM cells and sense amplifiers to a 1k-bit memory array. This includes schematics, layout, and post-layout simulation, as well as mastering Static Noise Margin (SNM) and process variation analysis. b. Engineering Mindset: The course fosters the ability to navigate PPA (Performance, Power, Area) design trade-offs, transitioning students from passive tool users to active logical debuggers. c. Employability: The final objective is to help students generate a chip design portfolio that meets industry standards, effectively closing the gap between academic learning and industrial application.

(Chinese) 電子學1,2 電路學1,2 固態電子學 (或 半導體元件物理) ------------------------------------- (English) Electronics 1, 2 Circuit Theory 1, 2 Solid-State Electronics (or Semiconductor Device Physics)

(Chinese) 本課程旨在解決記憶體設計課程中理論與實務脫節之問題。課程以「設計1k-bit SRAM IP」**為驅動主軸，引導學生遵循業界標準設計流程，從Schematic電路構思、Layout佈局繪製，推進至Post-Sim後模擬驗證。 教學過程中強調「做中學」與「設計權衡（Trade-off）」，要求學生利用HSPICE等EDA工具，針對速度、功耗與面積（PPA）進行優化分析。評量機制則突破傳統紙筆測驗，導入「多元評量」，包含除錯日誌、階段性實作檢核與期末效能競賽，藉此評估學生的問題解決邏輯與系統整合能力，並透過行動研究法之循環持續修正教學策略，以培育具備實戰力的IC設計人才。 (English) This course addresses the gap between theory and practice in memory design education. Centered around the project of designing a 1k-bit SRAM IP, the curriculum guides students through an industry-standard design flow—advancing from schematic conception and layout implementation to post-layout simulation (Post-Sim) verification. The instructional approach emphasizes 'learning by doing' and design trade-offs, requiring students to utilize EDA tools (such as HSPICE) to optimize for speed, power, and area (PPA). Moving beyond traditional written exams, the course adopts a multidimensional assessment strategy—including debugging logs, milestone implementation checks, and a final performance competition—to evaluate problem-solving logic and system integration capabilities. Furthermore, the course employs an action research cycle to continuously refine teaching strategies, ensuring the cultivation of industry-ready IC design talent.

(Chinese) 每周Homework佔30%，檢核除錯歷程；期中報告佔30%；期末專題佔40%，要求完成SRAM佈局與後模擬。評分導入業界PPA指標（效能、功耗、面積），透過競賽確保學生具備系統整合之實務能力。 (English) Grading Policy: Weekly Homework (30%): Focuses on verifying the debugging process and workflow. Midterm Report (30%). Final Project (40%): Requires the completion of SRAM layout and post-layout simulation. Note: Grading incorporates industry-standard PPA (Performance, Power, Area) metrics. A design competition format is used to ensure students possess practical skills in system integration.

(Chinese) 無。由授課教授自行編纂。 (English) None. Materials are compiled by the instructor.

地點

國立陽明交通大學光復校區工程四館。 Engineering Building 4, Guangfu Campus, National Yang Ming Chiao Tung University in Hsinchu City, Taiwan.

時間

請自行寄信給任課教授約時間。 (Please email the instructor to schedule an appointment.)

聯絡方式

謝易叡 副教授: erayhsieh@nycu.edu.tw