數位積體電路
Digital Integrated Circuits
| 節 | 週四 |
|---|---|
5 13:20–14:10 | 數位積體電路 EE205 3 節連堂 |
6 14:20–15:10 | |
7 15:30–16:20 |
* 根據陽明交大上課時間表所列
This course introduces the principles of modern digital integrated circuit design with a strong emphasis on the solid-state device physics underlying CMOS technologies. Students learn how electrostatics, carrier transport, short-channel effects, and parasitic elements influence inverter behavior, logic gate performance, power consumption, interconnect delay, and memory stability. Topics include CMOS inverter analysis, static and dynamic logic design, sequential circuits, interconnect modeling, low-power techniques, technology scaling, and SRAM design. Through lectures, homework, and SPICE simulations, students develop the ability to connect device-level characteristics to circuit-level metrics such as delay, noise margins, switching energy, and robustness.
To be announced later.
Midterm 30% Final 40% Homework 30%
| 週次 | 主題 |
|---|---|
| 第 1 週 | Introduction + Semiconductor Physics Review Crystal structure, doping, carrier statistics Drift, diffusion, continuity equations Intrinsic vs extrinsic semiconductor behavior |
| 第 2 週 | MOS Capacitor & Electrostatics MOS capacitor structure, band diagrams Depletion width, inversion conditions Threshold voltage derivation Effects of oxide thickness, doping, work function |
| 第 3 週 | MOSFET I–V, Transport Models, and Short-Channel Effects Drift–diffusion current derivation Mobility physics (phonon, Coulomb, surface roughness scattering) Velocity saturation, ballistic limits Short-channel effects: DIBL, CLM, VT roll-off |
| 第 4 週 | Device Parasitics and Capacitances Gate, overlap, fringing, Miller capacitances Junction capacitances: depletion approximation Parasitics and their physical origin in layout Impact on switching delay |
| 第 5 週 | Leakage Mechanisms & Device Reliability Subthreshold conduction (SS, Dit, interface traps) Gate leakage: direct tunneling through thin oxides Reliability: NBTI, PBTI, TDDB |
| 第 6 週 | CMOS Inverter: DC Characteristics VTC derivation using device I–V Noise margins, inverter sizing, body effect Relationship between VT, SCE, leakage and inverter transfer curve |
| 第 7 週 | CMOS Inverter: Switching Dynamics Current-based delay model Energy per transition, short-circuit current Technology scaling effects on inverter design |
| 第 8 週 | Power Dissipation & Energy Minimization Dynamic, short-circuit, and leakage power Physical origins of leakage and scaling challenges Energy–delay trade-off, VDD scaling |
| 第 9 週 | Combinational Logic (CMOS Static Logic) NAND/NOR transistor stack effects Logical effort from a device physics perspective Capacitance-driven vs current-driven delay |
| 第 10 週 | Pass-Transistor & Transmission-Gate Logic Vth drop and body effect in nMOS-only logic ON resistance and mobility asymmetry (µn vs µp) Charge sharing, leakage, robustness |
| 第 11 週 | Sequential Logic Devices Latches & flip-flops: dynamic storage physics Metastability analysis using device gain and regeneration Setup/hold derived from transistor-level timing |
| 第 12 週 | Interconnect Device Physics Metal resistivity, scattering mechanisms at small dimensions Line-edge roughness, variation, and statistical delay RC delay, coupling capacitance, crosstalk Technology scaling of interconnects |
| 第 13 週 | Technology Scaling & Advanced Transistors Constant-field scaling, voltage scaling limits Short-channel physics in FinFETs and nanosheet FETs Quantum confinement, ballistic transport Impact on digital design rules (VT, Ion, Ioff, parasitics) |
| 第 14 週 | Low-Power Design with Device Considerations Multi-threshold CMOS, sleep transistors Power gating, body biasing Device leakage engineering Physical limits of near-threshold and subthreshold logic |
| 第 15 週 | SRAM Device–Circuit Co-Design Read stability (SNM) tied to device current ratios Write-ability influenced by device overdrive and parasitics Variability impacts (VT mismatch, RDF) |
| 第 16 週 | Final Review Device physics → circuit metrics summary Deep dive: how modern CMOS device choices shape system efficiency |
Rabaey, Jan M.; Chandrakasan, Anantha P.; Nikolić, Borivoje. Digital Integrated Circuits: A Design Perspective. 2nd Edition, Pearson / Prentice Hall, 2003. ISBN-13: 9780131207646.
- 聯絡方式
- changchingtu@gmail.com