元件設計與模擬實驗
Device Design and Simulation Lab.
| 節 | 週六 |
|---|---|
2 09:00–09:50 | 元件設計與模擬實驗 3 節連堂 |
3 10:10–11:00 | |
4 11:10–12:00 |
* 根據陽明交大上課時間表所列
We learn how to use commercial available TCAD process and devicce simulators for design and simulation of emerging VLSI devices (mainly for MOSFETs/FinFET/GAA FETs, etc), III-V HEMTs, 2D-material FETs, etc. Stundets will be requested to hand on each lab in classes. We do not plan to discuss detail theory of TCAD simulation software. We mainly focus on hands-on simulation laboratories with introduction to execution instruction.
none
Basic concepts for all laboratories, TA demonstrations, hands-on your own lab., checks lab's results by TA on site, and submit your written report for that lab. after the class.
1. 10x5% = 50%; we will have ten labs and each lab has 5%. 2. Each enrolled student is required to conduct his/her own term project, it occupies 40% in total. 3. There is no midterm exam, but we have one final exam with open book. It is 10%.
- VLSI Process Simulation
- VLSI Device Simulation
- III-V HEMTs Simulation
- Emerging Device Simulation
| 週次 | 主題 |
|---|---|
| 第 1 週 | 一、前瞻所學生優先。有空位，會保留給114上學期有抽籤順位之同學。 二、2026/2/28為國定假日不上課，第一次上課為2026/03/07，為確保選課權益，請務必出席。 三、上課地點在電子資訊大樓5樓503室，由於一樓有門禁，請同學於8:30~8:55間抵達，並於教室入口處找助教簽到。 |
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We provide printed hardcopy lecture nortes for enrolled students.
- 地點
- Teacher office: M I S R C 8 2 1 R, National Yang Ming Chiao Tung University, Hsinchu 300093, Taiwan
- 時間
- Students are welcome to visit teacher's office on Wed. afternoon directly. You are encouraged to make an appointment for course discussion by email or office phone call.
- 聯絡方式
- Email: y m l i @ m a i l . y m l a b . o r g Office tel: 0 3 --- 5 7 1 2 1 2 1 Ext 5 2 9 7 4