封裝技術與設備
Packaging Technology and Equipment
| 節 | 週三 |
|---|---|
A 18:30–19:20 | 封裝技術與設備 EF207 3 節連堂 |
B 19:30–20:20 | |
C 20:30–21:20 |
* 根據陽明交大上課時間表所列
This course will teach the fundamentals for packaging, including phase diagrams of solders, bonding technology, metallurgical reactions, and reliabilities, as well as the state-of-the-art Cu-Cu hybrid bonding. It will also cover bonding technology of microelectronic packaging: Wire Bond, Tape automatic bonding, Flip Chip Technology, Ball Grid Array Technology, Pb-based and Pb-free Solders, 3D IC packaging, Cu-Cu bonding. Metallurgical reactions include Cu-Sn, Ni-Sn, Sn-Au, Ag-Sn, Pd-Sn, and In-Sn. The following reliability issues will be taught: multiple reflow, electromigration, thermomigration. Reliability analysis and wire bonding in power electronics will also be discussed. Heterogeneous integration, a promising packaging technology, unites mobile, HPCs, and AI applications. High-performance system-on-chips (SoCs) integrate energy-efficient memory with high bandwidth via HBMs, TSVs, and fine-pitch RDL, accommodating numerous I/Os. Semiconductor packaging, once overlooked, is now pivotal for SoC, wafer-level fanout packaging, 2.0/2.1/2.2/2.3/2.5D and 3DIC packing. Die-level stacking constraints 3D interconnect density due to I/O pad pitch. Wafer-to-wafer (W2W) stacking synchronizes pitch with CMOS back-end-of-line. interconnects, facilitating heterogeneous integration by stacking diverse device or sensor wafers. Hybrid W2W bonding, featuring a Cu/dielectric pattern, unleashes advanced functionality, outperforming conventional scaling in 3D SoC.
材導
1.學期作業 None 2.評量方法 Two midterms: 66.7%, Final: 33.3%
| 週次 | 主題 |
|---|---|
| 第 1 週 | Chip-level interconnection--Flip Chip Technology I-Introduction Reliability Pb-based and Pb-free solders, Metallurgical Reaction (I) bulk samples |
| 第 2 週 | Metallurgical Reaction (II) Thin Films Metallurgical Reaction (III) Reliability Issues of Pb-free Solder Joints, six cases solder FCT Reliability Metallurgical Reaction (IV): Cross reactions |
| 第 3 週 | Metallurgical Reaction (V): Effect of Solder Volume on Metallurgical reactions Effect of solder volume on the reliabilities of solder joints/microbumps. |
| 第 4 週 | Electromigration in solder joints |
| 第 5 週 | Midterm 1 |
| 第 6 週 | Advanced packaging introduction: SoC, wafer-level fanout packaging, 2.0/2.1/2.2/2.3/2.5D and 3DIC packaging |
| 第 7 週 | Advanced packaging process and facilities introduction: wafer-level fanout packaging, 2.5D and 3DIC packaging |
| 第 8 週 | Novelty of 3D wafer stacking: Low temperature wafer-to-wafer hybrid bonding |
| 第 9 週 | Introduction of the ECTC conference and latest technological advancements and innovative packaging techniques |
| 第 10 週 | Midterm 2 |
| 第 11 週 | Introduction and Overview of Packaging Technology and Process |
| 第 12 週 | Chip-level interconnection—Tape Automated Bonding and Wire Bonding: Process Technology and Application |
| 第 13 週 | Chip-level interconnection—Wire Bonding Technology: Advances and Challenges in Materials and Process Technologies |
| 第 14 週 | Break |
| 第 15 週 | Final Exam |
| 第 16 週 | Chip-level interconnection—Wire Bonding Technology: Reliability Analysis and Wire Bonding in Power Electronics |
Textbook: 1. K. N. Tu, Hung-Ming Chen, Chih Chen. Electronic Packaging Science and Engineering, Wiley 2021. 2. K. N. Tu, Solder Joint Technology: Materials, Properties, and Reliability (Springer 2007) Reference books: 1. 3D Microelectronic packaging: from fundamentals to applications, Editors: Li, Yan, Goyal, Deepak (Eds.), Springer. 2. “Electronic Packaging, Design, Materials, Process, and Reliability”John Lau, C.P. Wong, John L. Prince, and Wataru Nakayama, McGraw-Hill. 3. “Principles of Electronic Packaging ”Donald P. Seraphim, Ronald C. Lasky, Che-yu Li, McGraw-Hill, 1993. 4. “Flip chip technologies” John H. Lau, McGraw-Hill, 1996. 5. “Fundamentals of Microsystems Packaging”, R.R. Tummala, McGraw-Hill, 2001 6. 微電子材料與製程，陳力俊主編中國材料科學學會 2000 7. “Microelectronics packaging handbook” R.R. Tummala and E.J. Rymaszewski, Van Nostrand Reinhold, 1989. 8. Electronic Thin Film Science: For Electrical Engineers and Materials Scientists Tu, King-Ning/ Mayer, James W./ Feldman, Leonard C. 9. Fan-Out Wafer-Level Packaging, John H Lau, Springer, 2018.
- 地點
- EF310
- 時間
- TBA
- 聯絡方式
- 31814